Current-limiting layer and a current-reducing layer in a memory device

ABSTRACT

A current-limiting layer and a current-reducing layer are incorporated into a resistive switching memory device to form memory arrays. The incorporated current-limiting layer reduces the occurrence of current spikes during the programming of the resistive switching memory device and the incorporated current-reducing layer minimizes the overall current levels that can flow through the resistive switching memory device. Together, the two incorporated layers help improve device performance and lifetime.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.13/399,530, filed Feb. 17, 2012, now U.S. Pat. No. ______, which is acontinuation-in-part of co-pending U.S. patent application Ser. No.13/228,744, filed Sep. 9, 2011, now U.S. Pat. No. ______, and acontinuation-in-part of co-pending U.S. patent application Ser. No.13/353,000, filed Jan. 18, 2012, now U.S. Pat. No. 8,681,530, whichclaims benefit of U.S. Provisional Patent Application Ser. No.61/513,355, filed Jul. 29, 2011. Each of the aforementioned relatedpatent applications is herein incorporated by reference.

BACKGROUND

This invention relates to the formation of resistive switching memorydevices.

Nonvolatile memory devices are used in systems in which persistentstorage is required. For example, nonvolatile memory cards are used indigital cameras to store images and in digital music players to storeaudio data. Nonvolatile memory devices are also used to persistentlystore data in computer environments.

Electrically-erasable programmable read only memory (EEPROM) technologyis often used to form and program nonvolatile memory devices. This typeof nonvolatile memory contains floating gate transistors that can beselectively programmed or erased by application of suitable voltages totheir terminals. As fabrication techniques improve, it is becomingpossible to fabricate nonvolatile memory devices with increasinglysmaller dimensions. However, as device dimensions shrink, scaling issuespose challenges for traditional nonvolatile memory technology. This hasled to the investigation of other alternatives, including nonvolatileresistive switching memory technology.

Nonvolatile resistive switching memory device and system are formedusing memory cells that have two or more stable resistances states.Voltage pulses are used to switch the resistive switching memory elementfrom one resistance state to the other. For example, a bistable memorycell having a resistive switching memory element with two stableresistance states can be placed in a high resistance state or a lowresistance state by applying suitable voltages or currents.Nondestructive read and write operations can be performed to ascertainthe value of a data bit that is stored in a memory cell.

Resistive switching based on having a resistive switching memory elementformed of transition metal oxide (MO) films within a memory cell hasbeen demonstrated. A current steering element (typically a diode and/orresistor) can sometimes be integrated into a resistive switching memoryelement to direct current flow in a memory cell. Because the overallpower that can be delivered to a circuit containing a series ofconnected memory cells with resistive switching memory elements andcurrent steering elements is typically limited in most conventionalnonvolatile memory devices (e.g., CMOS driven devices), it is desirableto form each of the resistive switching memory elements and currentsteering elements in the circuit so that the voltage-drop across each ofthese elements is small, and thus the overall resistance of the seriesof these connected elements does not cause the current to decrease to anundesirable level when a high voltage level (e.g., ˜2-5 volts) isapplied.

As the sizes of the nonvolatile memory device shrink, it is important toreduce the required currents and voltages that are necessary to reliablyset, reset and/or determine the desired “On” and “Off” states of thememory device to minimize the overall power consumption of a memory chipas well as resistive heating of the devices within the memory chip andcross-talk between adjacent memory devices.

Moreover, it becomes increasing necessary to assure that the “set” and“reset” currents used to change the resistance state of the resistiveswitching memory element are not too large to alter the electrical orphysical properties of the one or more layers found in theinterconnected memory devices. A large current flowing through thecurrent carrying lines in a memory array can also undesirably alter ordisturb the “logic” state of the interconnected memory cells/devices orpossibly damage portions of the adjacently connected memory devices, dueto an appreciable amount of “cross-talk” between the formed devices.

Thus, there is a need to limit and/or minimize the required current usedto sense and program the logic states of each of the interconnectedmemory devices, in an effort to reduce chip overall power consumption aswell as improve device longevity and reduce the chance that cross-talkbetween adjacently connected devices. Therefore, it is desirable to forma nonvolatile memory device with a current-limiting material layer and acurrent-reducing material layer to minimize programming currents usedwhen switching the device between the “on” and “off” states.

SUMMARY

Embodiments of the invention generally include a method of forming aReRAM type nonvolatile memory device. The ReRAM type switching memorydevice includes at least one current-limiting layer and at least onecurrent-reducing layer integrated within or adjacent to a ReRAM typenonvolatile memory element. The ReRAM type switching memory element mayinclude a first electrode layer, a second electrode layer, and avariable resistance layer disposed between the first electrode layer andthe second electrode layer. In addition, the current-limiting layer andthe current-reducing layer can be incorporated into a number ofresistive switching memory devices within a memory array to help reducethe level of current flowing therein and minimize the memory array'soverall power consumption.

In one embodiment, the current-limiting layer is incorporated betweenthe variable resistance layer and at least one of a first electrodelayer and a second electrode layer. The incorporated current-limitinglayer reduces the magnitude of current spikes that are usually observedduring the programming of the resistive switching memory device.

In another embodiment, the current-reducing layer is incorporatedadjacent the variable resistance layer. In yet another embodiment, thecurrent-reducing layer is formed into a portion of the variableresistance layer. The incorporated current-reducing layer minimizes theoverall current levels that can flow through the resistive switchingmemory device.

In still another embodiment, the invention provides a method of forminga nonvolatile memory device including depositing a first electrodelayer, a second electrode layer, and a variable resistance layer betweenthe first electrode layer and the second electrode layer over a surfaceof a substrate. The method further includes depositing acurrent-reducing layer adjacent the variable resistance layer anddepositing a current-limiting layer between the variable resistancelayer and at least one of the first electrode layer and the secondelectrode layer.

In yet another embodiment, a method of forming a nonvolatile memorydevice having a nonvolatile memory element includes depositing a firstelectrode layer, a second electrode layer, and a variable resistancelayer between the first electrode layer and the second electrode layerover a surface of a substrate, forming a current-reducing layer into aportion of the variable resistance layer, and depositing acurrent-limiting layer between the variable resistance layer and atleast one of the first electrode layer and the second electrode layer.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentinvention can be understood in detail, a more particular description ofthe invention, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

FIG. 1 illustrates an array of resistive switching memory devices inaccordance with one embodiment of the invention.

FIG. 2A is a schematic representation of a memory device in accordancewith one embodiment of the invention.

FIG. 2B is a schematic representation of a memory device having a diodetype current steering element in accordance with another embodiment ofthe invention.

FIG. 2C is a schematic representation of an electrical circuit formed inaccordance with one embodiment of the invention.

FIG. 3A is a schematic cross-sectional view of a current-limiting layerand a current-reducing layer disposed in a nonvolatile memory device inaccordance with one embodiment of the invention.

FIG. 3B is a schematic cross-sectional view of a current-limiting layerand a current-reducing layer disposed in a nonvolatile memory device inaccordance with another embodiment of the invention.

FIG. 3C is a schematic cross-sectional view of a current-limiting layerand a current-reducing layer disposed in a nonvolatile memory device inaccordance with still another embodiment of the invention.

FIG. 3D is a schematic cross-sectional view of a current-limiting layerand a current-reducing layer disposed in a nonvolatile memory device inaccordance with yet another embodiment of the invention.

FIG. 4A is a graph illustrating the current (I) versus voltage (V)characteristics of the high and low resistance load lines of a variableresistance layer in accordance with an embodiment of the invention.

FIG. 4B is a current versus time plot illustrating the effect ofdelivering bipolar type switching pulses through a memory element inaccordance with an embodiment of the invention.

FIG. 5A illustrates the switching current levels of a conventionalnonvolatile memory device in accordance with one embodiment of theinvention.

FIG. 5B illustrates the switching current levels of a nonvolatile memorydevice having a current-limiting layer in accordance with anotherembodiment of the invention.

FIG. 5C illustrates the switching current levels of a nonvolatile memorydevice having a current-limiting layer and a current-reducing layer inaccordance with another embodiment of the invention.

DETAILED DESCRIPTION

Embodiments of the invention generally include a method of incorporatingat least one current-limiting layer and at least one current-reducinglayer into resistive switching memory devices disposed in an array ofmemory devices to eliminate undesirable current spikes, limit thecurrent flowing within the memory device during device switchingoperations, and further reduce the overall current levels that can flowwithin the memory device, thus improving the device performance andincreasing usable lifetime for each memory device.

In one embodiment, the current-limiting layer includes a resistorelement which comprises one or more layers of a resistive material thathas desirable electrical characteristics, such that currents flowingwithin the memory device are designed to be under a maximum devicecompliance level (e.g., less than a compliance current level (I_(CC)) asrequired by device specifications), thus limiting the chance of highcurrent spikes to cause damage to the memory device. Thecurrent-limiting layer provides added resistance to the memory device,which is much larger than the combined resistance of other componentswithin the memory device, such that currents flowing through the memorydevice during various device forming and switching operations arecontrolled by the presence of the resistance of the current-limitinglayer (e.g., a maximum current level at device “On” state equals anapplied voltage level divided by the resistance of the current-limitinglayer).

In one aspect, the electrical properties of the current-limiting layerhave a breakdown voltage that exceeds the breakdown voltage of thevariable resistance layer, thereby reducing the occurrence of currentspikes and limiting the magnitude of currents that can flow through thematerial layers of the nonvolatile memory device. The higher breakdownvoltage of the current-limiting layer helps to maintain resistance inthe memory device during the device electrical-forming stage and/orswitching operations and, as a result, reduce the chance of damage tothe memory device during high current switching operations. The effectof preventing device damage is due, in part, because it takes highervoltage levels to break down the materials within current-limitinglayer, as compared to the materials typically used in a variableresistance layer. Stated another way, the current-limiting layer iscapable of maintaining its resistance during various device forming andswitching operations, thereby limiting current flows and reducingcurrent spikes.

In another aspect, the total electrical resistance of thecurrent-limiting layer can be close to the electrical resistance of acurrent steering device of a ReRAM type switching memory device, such asbetween about 75% and about 125% of the resistance of the formed currentsteering element. It is found that the presence of the current-limitinglayer having a resistance near the resistance of the current steeringelement enable the current-limiting layer to function together with thecurrent steering element to enhance the switching performance in amemory device.

For example, the current-limiting layer may comprise a resistivematerial, such as a metal that has high resistivity, a dopedsemiconductor, and a conductive dielectric material, among others, so asto add a fixed series resistance in the formed nonvolatile memoryelement and limit the current flow through a variable resistance layerduring the logic state programming steps (i.e., “set” and “reset”steps).

One example of the suitable resistive material is a semiconductormaterial, for example, a polycrystalline silicon material (polysilicon).Other suitable materials include doped semiconductors, resistive metals,conductive dielectric materials, metal nitride materials,tantalum-containing materials, titanium-containing materials, siliconnitride, tantalum nitride, titanium nitride, hafnium nitride, germanium(Ge)-containing semiconductor materials, gallium arsenide, among others.The semiconductor material can be doped with a dopant, such asphosphorus (P), arsenic (As), antimony (Sb), boron (B), and aluminum(Al), among others.

In one aspect, the current-limiting layer acts as a resistive elementthat is connected with a formed resistive switching memory element of aresistive switching memory device to provide an additional resistanceduring normal device switching operations. In another aspect, thecurrent-limiting layer is a resistive element that is disposed within aresistive switching memory element in a nonvolatile resistive switchingmemory device. The incorporation of a simple, less complex resistiveelement into a resistive switching memory device that is easy tofabricate so that less complex devices can be formed.

In another embodiment, the current-reducing layer is an interfacialresistive layer disposed adjacent a variable resistance layer of anonvolatile memory element. The addition of the current-reducing layernear the variable resistance layer increases the total resistivity ofthe variable resistance layer and lowers the chance that large currents(e.g., I_(SET), I_(RESET), I_(ON), and I_(OFF)) can flow through thevariable resistance layer during device operation. The use of acurrent-reducing layer allows thinner layers to be used in the filmstack of the nonvolatile memory element, resulting in desirably lowerswitching currents in a ReRAM type switching memory device.

In forming the ReRAM type nonvolatile switching memory element, theaddition of the current-reducing layer can be used to increase thebarrier height at the interface between the variable resistance layerand electrode layers so as to reduce the current flowing through theresistive switching memory device. In one aspect, the current-reducinglayer is an interfacial layer formed: 1) adjacent to the variableresistance layer of a resistive switching memory device by chemicallytreating the variable resistance layer and/or 2) adjacent to theelectrode layer, so that the interfacial current-reducing layer can beformed between the variable resistance layer and the electrode layer. Inanother aspect, the current-reducing layer is formed into a portion ofthe variable resistance layer of a memory device by chemically treatingthe variable resistance layer or adding dopant atoms during thedeposition of the variable resistance layer.

For example, the current-reducing layer may be formed by doping aluminumor zirconium during the deposition of the variable resistance layer. Thecurrent-reducing layer may also be formed by depositing an interfacialhigh-k material layer between the variable resistance layer and one ormore electrode layers.

Alternatively, the current-reducing layer may be formed by chemicallytreating one or more silicon oxide-containing electrode layers with achemical oxidation solution or a buffered cleaning solution prior to orafter the formation of the variable resistance layer during thefabrication of the nonvolatile memory element.

In addition, the current-reducing layer may be formed by treating one ormore silicon oxide-containing electrode layers with ozone or nitrogenprior to the formation of the variable resistance layer. Thecurrent-reducing layer may also be formed by treating a portion or thebulk of the variance resistance layer after the formation of thevariable resistance layer.

The current-limiting layer and the current-reducing layer are integratedand both layers function together to improve the switchingcharacteristics of the ReRAM nonvolatile memory element. On one hand,the electrical properties of the current-limiting layer have a breakdownvoltage that exceeds the breakdown voltage of the variable resistancelayer, thereby limiting the currents that can flow through the ReRAMnonvolatile memory element.

In addition, the resistivity of the current-limiting layer materialand/or the thickness of the current-limiting layer are adjusted so thatthe electrical resistance of the current-limiting layer is between about75% and about 125% of the electrical resistance of the current steeringdevice, when current is flowing from the first electrode to the secondelectrode through the formed nonvolatile memory element.

On the other hand, a silicon oxide containing layer is formed adjacent(below or above) the variable resistance layer to reduce the overallmagnitude of current flowing through the switching memory device.Optionally, a high-k interfacial layer can be formed adjacent thevariable resistance layer or into a portion of the variable resistancelayer to serve as a current-reducing layer.

The addition of the current-reducing layer can lower the magnitude of acurrent flow that can flow through the switching memory device duringvarious device switching or programming operations and allow thinnerlayers to be used in the nonvolatile memory element, resulting indesirably lower switching currents and lower power consumption. It hasbeen found that the current-limiting layer and the current-reducinglayer can help minimize current spikes and high switching current levelsduring device operation and help improve device performance andlifetime.

The current-limiting layer and the current-reducing layer structure areincorporated into a nonvolatile memory device having a resistiveswitching memory element capable of switching between at least two ormore stable resistance states, each with a different resistance. Eachresistive switching memory device generally comprises an MIM(metal-insulator-metal) stack, wherein the insulator is a variableresistance layer that typically comprises a metal oxide material. Themetal oxide insulator offers bistable resistance for the resistiveswitching memory device.

A number of nonvolatile memory devices can be interconnected to form oneor more memory arrays prior to being connected to at least one controlcircuitry, and ultimately, fabricated into a memory array formed on amemory chip. Nonvolatile resistive switching memory devices may beformed as part of a high-capacity nonvolatile memory integrated circuit,which can be used in various electronic devices, such as digitalcameras, mobile telephones, handheld computers, and music players, amongothers.

Resistive Random Access Memory (RRAM or ReRAM) is often made byarranging a number of memory devices into cross point memory arrays toincrease the density of the memory devices connected together in memoryarray formed on a memory chip. A current steering element, such as adiode, is often used to prevent cross-talk between the interconnectedresistive switching memory devices from affecting the stored data inother interconnected memory devices within the memory array. The currentsteering element is configured to pass limited programming currentsthrough the resistive switching memory element in desired directions.

Even though significant progress has been made to reduce the compliancecurrent limit for a resistive switching memory device, the programmingcurrent levels for conventional memory devices are still much higherthan required levels to cause the switching memory devices to switch.For example, a resistive switching memory device may require its maximumprogramming current be under a compliance current limit of less than 10μA. Conventional resistive switching memory elements generally exhibitlarge magnitudes of current flowing therethrough, and most oftenencounter uncontrollable current spikes higher than desired switchingprogramming currents (e.g., high current levels and current spikes asshown as current levels 510 and current levels 504, respectively, inFIG. 5A and described in detail below).

It has been difficult to reduce the current levels and current spikes tobelow several tens of microamps so that they are under the I_(CC) limit.Previous solutions have used a single transistor in series with thememory element of the memory device, but this is generally notcompatible with the architecture of crossbar memory arrays, because thetransistors typically cannot be stacked vertically. In addition, suchapproaches require additional processing as well as additionalinterconnects to connect to the gate of the transistor.

Therefore, low switching currents can be achieved when uncontrolledcurrent spikes are eliminated and the magnitudes of the overall currentsflowing through the memory device are reduced during “switching” (SETand RESET) operations. In practice, it is very hard to prevent thecurrent spikes and large currents from flowing through the memorydevices due to the presence of parasitic capacitor-like elements foundin the interconnected memory array. These parasitic capacitor-likeelements are typically connected to the interconnected memory devicesand coupled to the electrodes of the memory devices, and tend to inducelarge currents independent of any control device separated from thememory element.

Accordingly, one embodiment of the invention integrates and incorporatesboth a current-limiting layer and a current-reducing layer in a memorydevice to resolve these parasitic currents. The incorporation of thecurrent-limiting layer in a memory device limits and/or minimizes thecurrent spikes during sensing and programming the logic states for eachof the interconnected memory devices, whereas the integration of thecurrent-reducing layer further reduces the magnitude of the currentflowing through each of the interconnected memory devices.

Together, the two layers reduce overall current levels during deviceswitching operations, reduce the memory chip's overall powerconsumption, improves device longevity, reduces the chance of cross-talkbetween adjacently connected memory devices, and thus minimizes thechance that cross-talk will alter the memory device's logic state. Thecurrent-limiting layer may be incorporated adjacent to the resistiveswitching memory element of a memory device, such as disposed “inseries” with or “within” a portion of the resistive switching memoryelement. The current-reducing layer is incorporated to be adjacent to orwithin a portion of the variable resistance layer within a switchingmemory element of a memory device.

Another embodiment of the invention provides for the setting of thecompliance current limit, I_(CC) or I_(MAX), at desirable switchingcurrents levels that meet the device specification requirements. Thecurrent-limiting layer and the current-reducing layer are disposedwithin each switching memory device to control and reduce the maximumcurrent flowing therethrough. In addition, the current-limiting layerand the current-reducing layer provided herein are designed to meet thecross-sectional requirements for dense flash memories. Thecurrent-limiting layer and the current-reducing layer are designed to becompatible with the use of a current steering element, which istypically a diode.

In addition, the current-limiting layer and the current-reducing layerare provided in memory devices having resistive switching memoryelements and current steering elements such that the voltage-drop acrosseach of these elements is small, and thus the overall resistance of theseries of these connected elements does not cause the current todecrease to an undesirable level due to a fixed voltage (e.g., between 2volts and 5 volts) applied to the memory circuit. Thus, thecurrent-limiting layer and the current-reducing layer are providedherein to form a nonvolatile memory device so that low programmingcurrents can be used to reliably switch the nonvolatile memory devicebetween the “on” and “off” device states.

The electrical properties of the current-limiting layer andcurrent-reducing layer are configured to lower the maximum current limitand the magnitude of the current that can flow through the variableresistance layer of the resistive switching memory element to preventthe transmitted current from damaging the memory device.

This objective is obtained, in part, by providing added resistances inthe formed nonvolatile resistive switching memory device, where theresistances are low at low voltage levels (e.g., the voltages appliedduring read operations) and the resistances are high at high voltagelevels (e.g., the voltages applied at set, reset, and switchingoperations).

It is generally desirable to form the current-limiting layer and thecurrent-reducing layer so that their material and electrical propertiesdo not degrade or breakdown during the often high current “burn-in” typedevice preparation steps, such as the “electrical forming” process, andalso during normal repetitive set, reset, or switching operations of thenonvolatile resistive switching memory device.

In one embodiment, by careful selection of the materials used to formthe material layers of the current-limiting layer and thecurrent-reducing layer described herein, the maximum current limit,I_(MAX), that is able to pass through the formed memory device isreduced so that the overall current levels used during normal deviceoperation and during the “electrical forming” process will meet thespecification requirement of device compliance current, I_(CC).

The careful selection of materials used will include the selection ofthe resistivity and thickness for each material layer, and the type andthe concentration of the dopant for each material layer, among others.The material layers of the resistor structure are selected and formed,and the currents flowing through the memory device are measured.

The resulting sense current measurements (by applying sensing pulses ata voltage level of V_(READ)) show that the measured current valuesduring “read” or “sensing” operations are reduced to near I_(ON) levelsand are kept relatively stable (e.g., no current spikes) after applyinghigh voltage levels applied during “set” or “switching” operations.

The incorporation of the current-limiting layer and the current-reducinglayer in a memory device allows the overall switching currents to belower than conventional memory devices, and in turn, allows for areduced overall operating power and the use of larger memory arraysizes.

FIG. 1 illustrates one example of a memory array 100 in accordance withone embodiment of the invention. The memory array 100 may be part of alarger memory device, system or other integrated circuit structures,such as a memory chip type device. The memory array 100 includes anumber of nonvolatile resistive switching memory devices, such as amemory device 200. In one aspect, the memory devices 200 can bespatially arranged as shown.

Alternatively, the memory devices 200 can be arranged in otherconfigurations. Each memory device 200 generally includes one or moreconductive layers. The one or more conductive layers may include anelectrode 102 and an electrode 118 disposed in the upper and lower sideof the memory device 200. Each conductive layer has a desired functionin the formed array of memory devices 200. The memory devices 200 can beaccessed individually or in groups using appropriate sets of word-linesand bit-lines, conveniently formed by the electrodes 102 and 118.

In one embodiment, the memory device 200 includes a current-limitinglayer 220, a current-reducing layer 230, a variable resistance layer206, and one or more material layers 114 to form into at least oneresistive switching memory element 112. For example, the resistiveswitching memory element 112 may contain an MIM stack, where aninsulator material layer is stacked between two or more conductive metalmaterial layers. The conductive metal material layers may be a topelectrode layer (e.g., the electrodes 102), an intermediate electrodelayer (e.g., an intermediate electrode layer 210 as shown in FIG. 2B), abottom electrode layer (e.g., the electrode 118).

The conductive metal material layers, such as the electrode 102, theintermediate electrode layer 210 and the electrode 118 are generallyformed from a conductive material, such as a highly conductivesemiconductor material (e.g., p-type polysilicon, n-type polysilicon)and/or a conductive metal material, e.g., titanium nitride (TiN),aluminum (Al), tungsten (W), among others, to minimize the circuitresistance created between the interconnected memory devices in thememory array 100. As an example, the insulator material layer may bestacked between the electrodes 102. 118, between the electrode 102 andan intermediate electrode layer 210, thus forming the MIM stack.

The variable resistance layer 206 may comprise a dielectric material,such as a metal oxide material or other similar material that can beswitched between at least two or more stable resistance states. Forexample, the variable resistance layer 206 may contain a metal oxidematerial, such as hafnium oxide (Hf_(x)O_(y)), tantalum oxide(Ta_(x)O_(y)), aluminum oxide (Al_(x)O_(y)), lanthanum oxide(La_(x)O_(y)), yttrium oxide (Y_(x)O_(y)), dysprosium oxide(Dy_(x)O_(y)), ytterbium oxide (Yb_(x)O_(y)) and zirconium oxide(Zr_(x)O_(y)), among others.

As another example, the variable resistance layer 206 may contain ametal nitride or metal silicate material, such as aluminum nitride(Al_(x)N_(y)), zirconium nitride (Zr_(x)N_(y)), silicon nitride(Si_(x)N_(y)), hafnium nitride (Hf_(x)N_(y)), aluminum oxynitride(Al_(x)O_(y)N_(z)), silicon oxynitride (SiON), hafnium oxynitride(Hf_(x)O_(y)N_(z)), hafnium silicon oxide (Hf_(x)Si_(y)O_(z)), zirconiumsilicon oxide (Zr_(x)Si_(y)O_(z)), hafnium silicon oxynitride (HfSiON),titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN),among others. In addition, the one or more material layers 114 maycontain a current steering element (e.g., a current steering element 216as shown in FIG. 2B).

In another embodiment, the current-limiting layer 220 comprises aresistive metal material, a doped semiconductor material, and aconductive dielectric material. The current-limiting layer 220 maycontain a polysilicon material, for example, an n-type semiconductormaterial, a p-type semiconductor material, a low bandgap semiconductormaterial (e.g., amorphous silicon, zinc oxide (Zn_(x)O_(y)), etc.).

Various doped polysilicon materials can be used to form thecurrent-limiting layer 220 by adjusting the concentrations of a dopant,such as phosphorus (P), arsenic (As), boron (B), aluminum (Al), etc. Inone example, polysilicon is a suitable material because its resistivitycan be modified by a suitable amount of doping, and it is asemiconductor material that can withstand high voltages and currentdensities.

As another example, the current-limiting layer 220 can be an N-typeresistor or a P-type resistor. As another example, the current-limitinglayer 220 may contain a metal nitride material (e.g., silicon nitride(Si_(x)N_(1-x)), hafnium nitride (Hf_(x)N_(y)), tantalum nitride(Ta_(x)N_(y)), titanium nitride (Ti_(x)N_(y)), etc.), a ternaryintermetallic material (e.g., tantalum silicon nitride(Ta_(x)Si_(y)N_(z)), titanium silicon nitride (Ti_(x)Si_(y)N_(z)),titanium aluminum nitride (Ti_(x)Al_(y)N_(z)), etc.), a ceramic metalalloy material (e.g., chromium silicon oxide (Cr_(x)Si_(y)O_(z))), amongothers.

In one example, the current-limiting layer 220 may be formed using anatomic layer deposition (ALD), chemical vapor deposition (CVD) orphysical vapor deposition (PVD) type process. In another example, thecurrent-limiting layer 220 comprises amorphous silicon, zinc oxide(Zn_(x)O_(y)), or chromium silicon oxide (Cr_(x)Si_(y)O_(z)) formedusing a PVD process. The thickness of the current-limiting layer may bebetween 50 angstroms and 1000 angstroms.

In still another embodiment, the current-reducing layer 230 is comprisedof an interfacial oxide-containing layer disposed between at least oneof the electrode layers and the variable resistance layer 206.Alternatively, the current-reducing layer 230 is an oxide-containinglayer formed into a portion of the variable resistance layer 206.

As an example, the current-reducing layer 230 may be a siliconoxide-containing layer formed by cleaning the surface of a siliconoxide-containing electrode layer (e.g., the electrode 210) with abuffered cleaning solution and/or chemically treating the siliconoxide-containing electrode layer with a chemical oxidation solutionprior to or after the formation of the variable resistance layer duringthe fabrication of the nonvolatile memory element.

In one example, the chemical cleaning solution may contain a mixture ofammonium hydroxide (NH₄OH), hydrogen peroxide (H₂O₂), and de-ionized(DI) water. As another example, the buffered cleaning solution may be anaqueous solution of hydrogen fluoride (HF) and deionized (DI) water andmay contain between about 0.1% and about 10% weight of hydrogen fluoride(HF) that is maintained at a temperature between about 20° C. and about30° C. As still another example, the buffered cleaning solution may be abuffered-oxide-etch (BOE) solution, such as a mixture of ammoniumfluoride (NH₄F) and hydrofluoric acid (HF).

As another example, the current-reducing layer 230 is formed using a dryclean procedure in a plasma processing chamber. In this embodiment, thesurface of a silicon-containing electrode layer may be exposed to aplasma comprised of ammonium (NH₃) and nitrogen trifluoride (NF₃)precursors to react with a native silicon oxide material found on thesurface of the silicon-containing material layer (e.g., the electrode102, 102B or the intermediate electrode layer 210) and form a highquality, thin silicon oxide-containing current-reducing layer thereon.The formed thin silicon oxide layer can be heated to a temperature ofabout 600° C. to about 800° C. for about 1 minute to about 10 minutes toimprove the quality of the formed silicon oxide layer.

As still another example, the current-reducing layer 230 may be asilicon oxide-containing layer formed by cleaning one or more siliconoxide-containing electrode layers with the wet cleaning solutions (e.g.,the chemical oxidation solution and the buffered cleaning solution asdescribed above) and treating the resulting cleaned silicon-oxidecontaining material layer with a plasma of ozone (O₃) or nitrogen (N₂),such as an ozone-containing plasma or a nitrogen-containing plasma,prior to or after the formation of the variable resistance layer 206.

As still another example, the current-reducing layer 230 may comprise adoped hafnium oxide layer formed by doping aluminum or zirconium into aportion of a hafnium oxide-containing variable resistance layer 206. Forexample, during the deposition of the variable resistance layer 206 overa surface of substrate, successive pulses of a dopant material (e.g.,aluminum or zirconium) can be introduced during an ALD, CVD, or PVDdeposition process prior to, or after, depositing the bulk of thehafnium oxide-containing variable resistance layer. The resulting dopedmetal oxide material layer region, which is formed into a portion of thebulk metal oxide containing variable resistance layer, serves as thecurrent-reducing layer 230 to help reducing the programming currentlevel flowing through a memory device thus formed.

The memory array 100 can be stacked in a vertical fashion or in otherconfigurations to form various types of multilayered memory arraystructures. The use of the resistive switching memory elements 112, thecurrent-limiting layer 220, the current-reducing layer 230, the variableresistance layer 206, and the one or more materials layers 114, to formmemory arrays as shown in FIG. 1, is merely illustrative, and oneskilled in the art would appreciate that the formed devices may be usedin other device applications without deviating from the basic scope ofthe invention described herein.

FIGS. 2A and 2B illustrate two examples of the memory device 200. Thememory device 200 includes the electrode 118 disposed over a surface ofa substrate 201, a variable resistance layer 206 disposed over thesurface of the electrode 118, a current-reducing layer 230 disposedadjacent the variable resistance layer 206, a current-limiting layer 220disposed over the surface of the current-reducing layer 230 and anelectrode 102 disposed over the surface of the current-limiting layer220.

In one aspect, as shown in FIG. 2B, the electrodes 102 and 118 eachinclude two or more conductive layers in which a first conductive layer(e.g., electrode layers 102A, 118A) is used to interconnect a number ofthe memory devices 200, and a second conductive layer (e.g., electrodelayers 102B, 118B) is disposed in each memory device 200 to provide adesirable electrical interface (e.g., desirable work function) to theadjacent components in the memory device 200.

In addition, an intermediate electrode layer 210, as shown in FIG. 2B,is disposed near the variable resistance layer 206 to provide adesirable electrical interface (e.g., desirable work function). Forexample, the intermediate electrode layer 210 can be provided as a metallayer for the MIM stack of the resistive switching memory element 112.

The memory device 200, as shown in FIGS. 2A-2B, includes a resistiveswitching memory element 112 and, optionally, a current steering element216 which allows current to flow through the memory device 200,preferentially in a forward direction (“I+”). In one configuration, thecurrent steering element 216 is an intervening electrical component,such as a p-n junction diode, p-i-n diode, transistor, or other similardevice that is disposed between the bottom electrode layer 118 and theresistive switching memory element 112.

Alternatively, the current steering element 216 can also be disposedbetween the top electrode layer 102 and the resistive switching memoryelement 112. For example, the current steering element 216 may includetwo or more layers of semiconductor material, such as two or moreP-doped or N-doped silicon layers, configured to direct (e.g., allow orinhibit) the current flow through the memory device 200 in differentdirections during operation.

In one example, the current steering element 216 is a diode thatcomprises a p-doped silicon layer (not shown), an un-doped intrinsiclayer (not shown), and an n-doped silicon layer (not shown) that has anoverall resistance between about 1 kΩ and about 100 MΩ. The overallresistance of the current steering element 216 generally depends on thetype of current steering element 216 that is formed and in whatdirection current is flowing through the memory device 200 (e.g.,forward or reversed biased).

Alternatively, a high-capacity nonvolatile memory integrated circuit maycontain a MOS-type transistor or other types of transistors to regulatecurrent flow. Because of the design of the material layers withincurrent steering element 216, a reduced current can also flow in theopposing direction through the memory device 200 by the application of areverse bias to the electrodes 102 and 118.

The electrodes 102, 118, 102A, 102B, 118A, 118B and 210 disposed in thememory device 200, as shown in FIGS. 1, 2A-2B, are generally formed froma conductive material that has a desirable conductivity and workfunction. In some configurations, these electrodes may be formed fromdifferent materials, which may include, but are not limited to p-typepolysilicon, n-type polysilicon, transition metals, transition metalalloys, transition metal nitrides, and transition metal carbides.

In one example, the electrodes comprise a metal, metal alloy, metalnitride or metal carbide formed from an element selected from a groupconsisting of titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co),molybdenum (Mo), nickel (Ni), vanadium (V), hafnium (Hf) aluminum (Al),copper (Cu), platinum (Pt), palladium (Pd), iridium (Ir), ruthenium(Ru), and combinations thereof. In one example, the electrodes 102, 118,102A, 102B, 118A, 118B and 210 comprise a metal alloy selected from thegroup of a titanium/aluminum alloy, transition metal nitride (e.g.,titanium nitride (TiN), tantalum nitride (TaN), or a silicon-dopedaluminum (AlSi)).

In another example, the electrodes 102, 118 may comprise a transitionmetal, transition metal alloy, transition metal carbide, transitionmetal nitride (e.g., titanium nitride (TiN), tantalum nitride (TaN)),and the intermediate electrode layer 210 comprises a heavily dopedsemiconductor material, such as a heavily doped silicon material (e.g.,n-type polysilicon material) that interfaces well with the currentsteering element 216.

For example, the intermediate electrode layer 210 may comprise apolysilicon material and is between about 50 and about 500 angstromsthick, and the electrodes 102, 118 are between about 50 angstroms and5000 angstroms thick and comprise a conductive metal material, such astitanium nitride (TiN). The electrodes 102, 118, 102A, 102B, 118A, 118Band 210 can be formed over a surface of a substrate 201 by a depositionprocess, including CVD (e.g., low pressure CVD (LPCVD), plasma enhancedchemical vapor deposition (PECVD)), ALD (e.g., plasma enhanced atomiclayer deposition (PEALD)), PVD, liquid deposition processes, ionimplants, and epitaxial processes to a thickness from 50 angstroms to500 angstroms.

FIG. 2C schematically illustrates an electrical circuit formed in thememory device 200, according to one or more embodiments of theinvention. The memory device 200 is generally coupled to aread-and-write circuitry 150 using word-lines and orthogonal bit-lines(generally referred herein as the electrodes 102 and 118) used to readfrom or write data into the memory devices 200.

A plurality of the electrodes 102 and 118, bit lines, word lines, andsource-lines within the memory arrays are typically biased by at leastone current or voltage delivering device, such as the read-and-writecircuitry 150. The arrays of the memory devices 200 are generallyconnected to the read-and-write circuitry 150, which is often connectedto connection points located at the periphery of a memory chip. Forexample, the electrodes 102 and/or 118 can be biased by theread-and-write circuitry 150.

In one embodiment, at least one current-limiting layer 220 and at leastone current-reducing layer 230 are incorporated into each of the memorydevices 200 to control the current flowing therethrough when a pulse ofenergy, such as a voltage pulse or current pulse, is applied by theread-and-write circuitry 150 during the electrical forming process,sensing process, or device programming operations.

The electrical circuit within the memory device 200 includes: a topelectrode impedance (e.g., resistance R₆) created by the materiallayer(s) in the electrode 102, a variable resistance layer impedance(e.g., resistance R₅) created by the material layer(s) in the variableresistance layer 206, a current-reducing layer impedance (e.g.,resistance R₄) created by the material layer(s) in the current-reducinglayer 230, a current-limiting layer impedance (e.g., resistance R₃)created by the material layer(s) in the current-limiting layer 220, acurrent steering element impedance (e.g., resistance R₂) created by thematerial layer(s) in the current steering element 216, and a bottomelectrode impedance (e.g., resistance R₁) created by the materiallayer(s) in the electrode 118. Additionally, the electrical circuit ofthe memory device 200 may also include an intermediate electrodeimpedance (e.g., resistance R_(IEL)) created by the material layer(s) inthe intermediate electrode layer 210.

FIGS. 3A-3D schematically illustrate cross-sectional views of fourexamples of the memory devices 200 having at least one current-limitinglayer 220 and at least one the current-reducing layer 230 disposedwithin two electrodes (e.g., the electrodes 102 and 118 of the memorydevice 200), according to one or more embodiments of the invention. Theexamples here are merely illustrative and not an exhaustive list of allexamples. In general, one or more material layers used to form thememory device 200 is formed over, or integrated with and disposed over,a portion of the surface of the substrate 201, which can be for example,any semiconductor wafers, semiconductor substrates, silicon substrates,SOI substrates, among others.

In one embodiment, the current-limiting layer 220 is disposed within theelectrodes of the memory device 200 close to (e.g., adjacent, next to,near, over, atop, under, below) the variable resistance layer 206 and/orcurrent steering device 216 to effectively limit current spikes orprevent programming currents delivered through the memory device 200from damaging the layers formed therein during normal device operation.

In one example, as shown in FIG. 3A, the current-limiting layer 220 isformed within the MIM stack of the resistive switching memory element112, such as being disposed between the electrode 102B and the variableresistance layer 206, over the surface of a substrate 201. Thecurrent-limiting layer 220 may be a resistive material-containing layerdeposited to a thickness of between 50 angstroms and about 500 angstromsover the surface of the variable resistance layer 206 using a depositionprocess, such as an ALD, CVD, PVD or other similar process.

In another example, as shown in FIG. 3B, the current-limiting layer 220is disposed between the electrodes 102A, 102B by depositing a resistivematerial-containing current-limiting layer 220 over the surface of theelectrode 102B using an ALD, CVD, PVD or other similar process. In yetanother example, as shown in FIG. 3C, the current-limiting layer 220 isdisposed between the electrode 118B and the variable resistance layer206 by depositing a resistive material-containing current-limiting layer220 over the surface of the electrode 118B using an ALD, CVD, PVD orother similar process In the example of FIG. 3D, the current-limitinglayer 220 is disposed between the electrodes 118A, 118B by depositing aresistive material-containing current-limiting layer 220 over thesurface of the electrode 118A using an ALD, CVD, PVD or other similarprocess.

In another embodiment, the current-reducing layer 230 is adjacent to(e.g., next to, near, over, above, atop, under, below) the variableresistance layer 206, such as between the variable resistance layer 206and an electrode layer (e.g., the electrodes, 102, 102B, 118, 118B, 210)or is formed into a portion of the variable resistance layer 206 toreduce the magnitude of the programming currents delivered through thememory device 200.

In the example as shown in FIG. 3A, the current-reducing layer 230 isdisposed adjacent to the variable resistance layer 206 (e.g., betweenthe variable resistance layer 206 and the electrode 118B). In thisconfiguration, the current-reducing layer 230 can be formed bychemically treating the surface of the electrode 118B with a bufferedcleaning solution or a chemical oxidation solution, as discussed below.

For example, the electrode 118B may be a silicon-containing materiallayer and the surface of the electrode 118B may be cleaned with abuffered cleaning solution to form a thin native silicon-oxide layer andserve as the current-reducing layer 230. The buffered cleaning solutioncan be any suitable cleaning solution for cleaning the surface of asurface known in the art, for example, the buffered cleaning solutionmay contain one part of about 49% of hydrogen fluoride (HF) and one partof distilled water, resulting in a water solution of about 24.5% (about14.2 mol/L) of hydrogen fluoride.

As another example, the buffered cleaning solution may be a dilutedhydrogen fluoride (DHF) solution, which contains 1:200 of HF:water. Asstill another example, the buffered cleaning solution may be a bufferedhydrogen fluoride (BHF) solution, which contains seven parts of about40% of NH4F and one part of about 49% (about 28.4 mol/L) of hydrogenfluoride (HF). As still another example, the buffered cleaning solutionmay contain two parts of BHF mixed with one part of glycerol.

In general, a substrate having a surface of the electrode 118B may beput in the cleaning solution for a period of time before being rinsed ina solution of distilled water and dried with a nitrogen gun.Alternatively, the surface of the electrode 118B may be cleaned by avapor of HF and water in a substrate processing system, where nitrogengas is bubbled at 0.1 to 1 liter/min through a 49% HF solution togenerate a vapor of HF and water for etching and cleaning the surface ofthe electrode 118B.

As another example, by providing an electrode (e.g., the electrode 118B)that comprises a silicon material or an electrode that has been cleanedwith a buffered cleaning solution to have a thin layer of a nativesilicon oxide material formed thereon), the surface of the electrode(e.g., the electrode 118B) can be treated with a chemical oxidationsolution to further form a thin layer of silicon oxide of about 5angstroms to about 20 angstroms.

The film quality of the formed, chemically oxidized thin layer ofsilicon oxide is good to be used as the current-reducing layer 230. Thechemical oxidation solution used to form the thin layer of silicon oxidecan be any suitable chemical cleaning solution for cleaning the surfaceof a surface known in the art, for example, the chemical cleaningsolution may contain a mixture of ammonium hydroxide (NH₄OH), hydrogenperoxide (H₂O₂), and de-ionized (DI) water. The ratio of NH₄OH to H₂O₂to DI water may be from about 1:1:5 to about 1:4:50.

As still another example, the electrode 118B may comprise asilicon-containing material and a substrate fabricated with thesilicon-containing electrode 118B can be placed inside asubstrate-processing chamber (e.g., an ALD or CVD substrate processingchamber and treated with ozone (O₃) gas a temperature of about 200° C.to about 350° C. for about 1 minute to about 60 minutes to form a thinlayer of silicon oxide over the surface of the silicon-containingelectrode 118B to be used as the current-reducing layer 230.

As still another example, the cleaned surface of the electrode 118B mayform a native silicon oxide layer and may be further treated with anitrogen-containing (N₂) plasma a temperature of about 20° C. to about300° C. for about 30 seconds to about 500 seconds inside asubstrate-processing chamber.

In an alternative example, in the same configuration of FIG. 3A, thecurrent-reducing layer 230 may comprise a doped metal oxide materialformed by ALD, CVD, PVD, or other similar process. In one example, thecurrent-reducing layer 230 is formed by depositing a metal oxide film byCVD, doping the metal oxide film with a dopant, such as zirconium (Zr)or aluminum (Al) to an appropriate dopant level of between about 1×10¹⁶atoms/cm³ and about 1×10¹⁹ atoms/cm³ (e.g., between about 1×10¹⁶/cm³ andabout 5×10¹⁷ atoms/cm³).

Alternatively, doping of the current-reducing layer 230 may be performedafter current-reducing layer 230 is deposited (e.g., doping a depositedfilm by an ion implant process). As an example, a metal oxide layer canbe deposited and doped with a dopant in a CVD deposition process to athickness of between about 5 angstroms and about 15 angstroms at atemperature of 300° C. or above, such as between 580° C. and 650° C.

Alternatively, a dopant can be introduced during the deposition of themetal oxide layer. For example, the current-reducing layer 230 maycomprise a doped hafnium oxide material formed to a thickness of betweenabout 5 angstroms and about 15 angstroms, such as an aluminum dopedhafnium oxide layer or a zirconium doped hafnium oxide layer.

In one example, the current-reducing layer 230 may be a doped hafniumoxide material layer deposited as a portion of a hafniumoxide-containing variable resistance layer during the deposition of thehafnium oxide-containing variable resistance layer 206 over the surfaceof the electrode 118B. A dopant material, such as aluminum or zirconium,can be introduced into an ALD or CVD process chamber together withprocess gasses for depositing a hafnium oxide variable resistance layer206 until a thickness of between about 5 angstroms and about 15angstroms of doped hafnium oxide is obtained.

Once the doped hafnium oxide material layer is formed to the desiredthickness, the bulk of the variable resistance layer 206 can beconveniently deposited in the same deposition chamber by stopping theflow of the dopant and continuously delivering the process gases forhafnium oxide into the deposition chamber.

Alternatively, the doped hafnium oxide-containing current-reducing layercan be deposited as a separate thin layer over the surface of theelectrode 118B prior to depositing the variable resistance layer 206 byintroducing a dopant together with process precursors for metal oxideinside an ALD, CVD, PVD or similar deposition chamber.

Next, the variable resistance layer 206 is deposited using an ALD, CVD,PVD or other similar process. Once the variable resistance layer 206 isdeposited, the current-limiting layer 220 can be deposited over thesurface of the bulk of the variable resistance layer 206, and then theelectrodes 102B, 102A can be deposited over the current-limiting layer220.

To further enhance the film quality of the formed current-limiting layer220 and the formed current-reducing layer 230, the deposited materiallayers can be subjected to various post-deposition treatment processes.As an example, the surface of the electrode 118B may be cleaned with acleaning solution to form a thin layer of silicon-oxide containingcurrent reducing layer 230 and further treated with an ammonium(NH₃)-containing solution or a plasma containing nitrogen (N₂) or oxygen(O₂) to enhance the film quality of the formed thin layer ofsilicon-oxide containing current-reducing layer 230.

As another example, once the current-limiting layer 220 and/or thecurrent-reducing layer 230 are deposited on the substrate 201, thesurface of the substrate 201 can be subject to a post-depositionannealing process (e.g., rapid thermal anneal with oxygen rich ambient,rapid thermal anneal with nitrogen rich ambient, rapid thermal annealwith an ambient of about 96% hydrogen and 4% argon forming gases, rapidthermal anneal with argon gas, among others.) in an substrate processingchamber (e.g., a rapid thermal oxidation (RTO) chamber, a rapid thermalnitradation (RTN) chamber, a rapid thermal anneal (RTA) chamber, amongothers.)

In the example as shown in FIG. 3B, the current-reducing layer 230 isdisposed close to or adjacent (e.g., next to, near, over, above, atop,under, below) the variable resistance layer 206, such as between thevariable resistance layer 206 and an electrode layer (e.g., theelectrodes 102, 102B, 118, 118B, 210) or it can be formed into a portionof the variable resistance layer 206 to reduce the magnitude of theprogramming current delivered through the memory device 200.

The current-reducing layer 230 may be deposited over the surface of theelectrode 118B prior to depositing the variable resistance layer 206,the electrode 102B, and the electrode 102A over the surface of thesubstrate 201. The example of FIG. 3B differs from the example of FIG.3A in that the current-limiting layer 220 is deposited over the surfaceof the deposited electrode 102B and is thus disposed in series with theMIM stack of the resistive switching memory element 112 to limit thecurrent flowing through the resistive switching memory element 112.

In the example as shown in FIG. 3C, the current-reducing layer 230 isdeposited adjacent (e.g., next to, near, over, above, atop, under,below) the variable resistance layer 206, such as between the variableresistance layer 206 and an electrode layer (e.g., the electrodes 102,102B, 118, 118B, 210) or is formed into a portion of the variableresistance layer 206 to reduce the magnitude of the programming currentsdelivered through the memory device 200.

In this configuration, the current-reducing layer 230 can be formed overthe surface of the variable resistance layer 206 using an ALD, CVD, PVDor other substrate treatment solutions and processes as described abovein the example of FIG. 3A. For example, the current-reducing layer 230may comprise an oxide-containing material layer formed over the surfaceof the substrate 201 by treating the metal oxide-containing variableresistance layer 206 with a cleaning solution (e.g., a buffered cleaningsolution or a chemical cleaning solution as described above) to form athin native silicon-oxide layer that serves as the current-reducinglayer 230.

Alternatively, the current-reducing layer 230 may comprise a doped metaloxide material formed in the same or different ALD, CVD, PVD, or othersimilar process chamber for depositing the bulk of the variableresistance layer 206. A metal oxide containing variable resistance layer206 can be deposited to a thickness from about 10 angstroms to 5000angstroms at a temperature of 300° C. or above, such as between 580° C.and 650° C., and a portion of the variable resistance layer 206 can bedoped with a dopant (e.g., aluminum or zirconium, among others) in thesame or different CVD deposition process to a thickness from about 10angstroms to 500 angstroms at a temperature of 300° C. or above, such asbetween 580° C. and 650° C.

In the example as shown in FIG. 3C, the current-limiting layer 220 isdisposed between the electrode 118B and the variable resistance layer206 prior to depositing the current-reducing layer 230 comprising asilicon oxide or doped hafnium oxide material.

In the example as shown in FIG. 3D, the current-reducing layer 230 isdisposed close to or adjacent (e.g., next to, near, over, above, atop,under, below) the variable resistance layer 206, such as between thevariable resistance layer 206 and an electrode layer (e.g., theelectrodes 102, 102B, 118, 118B, 210) or is formed into a portion of thevariable resistance layer 206 to reduce the magnitude of the programmingcurrents delivered through the memory device 200.

In this configuration, the resistive material-containingcurrent-limiting layer 220 is disposed between the electrodes 118A, 118Band the current-reducing layer 230 is formed over the surface of theelectrode 118B using an ALD, CVD, PVD or other substrate treatmentsolutions and process techniques as described above in the example ofFIG. 3A.

To obtain the current-limiting layer 220 and the current-reducing layer230 as described in FIGS. 1A-1B, 2A-2B, 4A-4B and 6 with desirableelectrical and/or physical properties, one or more steps can be adjustedin a deposition process to form the material layers within the memorydevice 200.

In some cases it is desirable to adjust the resistivity (ρ) andthickness (L) of the current-limiting layer 220 and the current-reducinglayer 230 so that the resistance (R₃) of the current-limiting layer 220and/or the resistance (R₄) of the current-reducing layer 230 is designedto match the resistance of the formed current steering element 216 inthe formed memory device 200.

One skilled in the art will appreciate that the resistance (R) tocurrent flow through a thin film is equal to the resistivity (p) of thefilm times the length (L) of the film divided by its cross-sectionalarea (A), or resistance R=ρ(L/A), where the length “L” is the thicknessof the layer that the current flows through and the cross-sectional area(A) is measured perpendicular to the current flow direction (e.g.,perpendicular to the thickness direction).

Resistivity (ρ) is an intrinsic property of the formed layer that can beadjusted in some cases by adjusting the composition of the layer, suchas adding alloying elements or doping atoms, or by adjusting thecrystalline structure of the layer (e.g., crystal structure).

Because the cross-sectional area (A) of the memory device is generallyfixed by the size and lateral spacing of the memory devices 200 formedon a memory chip, and thus is generally not easily varied from onememory device to the next, thus, the resistance of the current-limitinglayer 220 and the current-reducing layer 230 can be controlled by theadjustment of the thickness “L” and/or the resistivity (ρ) of thecurrent-limiting layer 220 and the current-reducing layer 230.

Typical deposition processes may include ALD, PVD and CVD processes thatcan be tailored to adjust the material resistivity and thickness of thedeposited material layers within the current-limiting layer 220 and thecurrent-reducing layer 230. In general, the current-limiting layer 220and the current-reducing layer 230 as shown in FIGS. 3A-3D can bedeposited using a deposition process, including but not limited to, CVD(e.g., LPCVD, PECVD), ALD (e.g., PEALD), PVD, liquid depositionprocesses, ion implants, and epitaxial processes, among others.

In addition, the current-reducing layer 230 can be formed adjacent thevariable resistance layer 206 by various post-deposition substratetreatment solutions and processes as described above. The thickness ofthe current-limiting layer 220 may be between about 10 angstroms and1000 angstroms and the thickness of the current-reducing layer 230 maybe between about 10 angstroms and 1000 angstroms.

To effectively reduce current spikes and limit current flowing throughthe resistive switching memory element 112. For example, thecurrent-limiting layer 220 and the current-reducing layer 230 can bedeposited with a resistivity of between about 1 Ω-cm and about 10 Ω-cm,which depends on its thickness, device geometry, and devicespecification requirements.

For a device specification of a switching voltage of 2 volts (V) andmaximum current of 10 μA, the total resistance of the memory devicerequired under the device specification is about 200 KΩ. As a result,the current-limiting layer 220 can have low resistance of between about10 KΩ and about 200 KΩ at a thickness of between 15 angstroms and about150 angstroms and the current-reducing layer 230 can have a thickness ofbetween 5 angstroms and about 20 angstroms to meet the complianceprogramming current levels of below 10 μA (e.g., between about 1 μA andabout 10 μA) and a switching voltage level ranging from 1V to 10V.

For example, the resistance of the current-limiting layer 220 may beadjusted to provide the total resistance of the memory device (e.g., aresistance of 100 KΩ provided by the current-limiting layer 220 as thedevice resistance during a “reset” operation). In addition, as shown inFIGS. 3A-3D, the current-limiting layer 220 can be disposed “in series”or “within” the layers of the resistive switching memory element 112 tolimit current and reduce the magnitude of any current spikes, and thecurrent-reducing layer 230 is disposed “within” the layers of theresistive switching memory element 112 to limit current and reduce themagnitude of the current levels flowing through the resistive switchingmemory element 112.

It is noted that the order of performing the deposition steps depends onthe design choice in forming the memory device. For example, thecurrent-limiting layer 220 and the current-reducing layer 230 can beformed prior to, or after, the variable resistance layer 206 isdeposited. In addition, the electrode layers (e.g., the electrodes 102,118, 210, 102A, 102B, 118A and/or 118B disposed in the memory device 200as shown in FIGS. 1, 2A-2C, 3A-3D) can be deposited prior to, or after,the current-limiting layer 220 and the current-reducing layer 230 areformed.

In addition, the entire material stack of the memory device 200 can besubject to a post-deposition annealing treatment. The annealingtreatment of the deposited material layers of the memory device 200 maybe performed, for example, at high temperature of between 200° C. and750° C. and for a period of time (e.g., between 1 minute and 5 minutes).Annealing is used to activate the materials within layers and enhanceadhesion between the layers.

According to one embodiment of the invention, the resistive switchingmemory elements 112 as shown in FIGS. 1, 2A-2C, 3A-3D is a bistablememory element having two stable resistance states, which may include ahigh resistance state (HRS) and a low resistance state (LRS), byapplying suitable voltages or currents. The resistive switching memoryelements 112 of the memory device 200 may use bipolar switching, whichuses set and reset voltages (V_(SET) and V_(RESET)) having oppositepolarities to alter the resistance of the resistive switching memoryelement 112 between the high and low resistance states.

Conventional Resistive Switching Memory Devices

FIG. 4A schematically illustrates exemplary log-log plots of measuredcurrent (I) values versus applied voltages (V) of a memory device havinga resistive switching memory element 112 having two bistable resistivestates, a low-resistance-state (LRS) curve 430 and ahigh-resistant-state (HRS) curve 420. By sweeping the voltage applied tothe electrodes 102 and 118 between two applied voltages (e.g., betweenV_(SET) (e.g., −3 volts) and V_(RESET) (e.g., +4 volts)) while thememory device is in the low resistance state, the LRS curve 410 can becreated. On the other hand, by sweeping the voltage applied to theelectrodes 102 and 118 between two applied voltages (e.g., betweenV_(SET) and V_(RESET)) while the device is in the high resistance state,the HRS curve 420 can be created.

Accordingly, the resistive switching memory element 112 of a memorydevice may either be in a high resistance state (HRS) or a lowresistance state (LRS). The resistive switching memory elements 112within a memory device can be selectively chosen by the read-and-writecircuitry 150 to switch between its resistance states. The currentsteering element 216 is used to regulate (e.g., allow or inhibit, etc.)the currents flowing through only the desired memory elements when theappropriate set of word-lines and bit-lines and/or electrodes areselected.

Depending on the physical and electrical characteristics of the variableresistance layer 206, the memory device will switch from the HRS to theLRS (i.e., arrow 421) during a “set” operation when a V_(SET) isapplied. On the contrary, the variable resistance layer 206 of thememory device will function to switch from the LRS to the HRS (i.e.,arrow 431) during a “reset” operation when a V_(RESET) is applied.

FIG. 4B is a plot of current versus time for a plurality of bipolar type“set” and “reset” switching pulses delivered to a memory device, asillustrated by pulses 401, 402, 403, 404, 405, and 406, in accordancewith an embodiment of the invention. Initially, in an effort to preparethe resistive switching memory element 112 for use, it is common toapply a forming voltage (V_(FORM)) at least once across the electrodes102 and 118 to “burn-in” the memory device, prior to a series ofprogramming “read” and “write” operations.

In one example, as shown in FIG. 4B, a device programming step mayinclude the delivery of a “set” switching pulse 411, a “reset” switchingpulse 413, and two “sensing” pulses 412. To assure that the memoryelement 112 reliably switches from a high resistance state (HRS) to alow resistance state (LRS) and vice versa, one must assure that the“set” switching pulse 411 produces a current that is greater than aminimum “set” current I_(MSC), which is defined as the minimum currentrequired to flow through the variable resistance layer 206 to cause itto switch from a high resistance state (e.g., 2.5 MΩ) to a lowresistance state (e.g., <<250 kΩ). In one example, the high and lowresistance states of the variable resistance layer 206 may be about 2.5MΩ and about 100 kΩ, respectively.

In addition, to assure that the resistive switching memory element 112reliably switches from a low resistance state to a high resistancestate, the “reset” switching pulse 413 is generally delivered at acurrent level that is greater than a minimum “reset” current, I_(MRC),which is defined as the minimum current required to flow through thevariable resistance layer 206 to cause it to switch from a lowresistance state to a high resistance state.

It should be noted that the minimum “set” current, I_(MSC), and theminimum “reset” current, I_(MRC), are related to the physical and/orelectrical properties of the material within the variable resistancelayer 206, and thus may be adjusted by careful selection of thematerial(s) and/or physical properties (e.g., thickness) of the variableresistance layer 206 and by performing various post-processing stepsafter forming the variable resistance layer within the stack of theresistive switching memory element 112.

Referring to FIG. 4A, in one example, when a “set” switching pulse 411is delivered through a standard switching memory device, the memorydevice will switch from the high-resistance-state (HRS) to thelow-resistance-state (LRS), as shown by the arrow 421. One will notethat the current flowing through a memory device will shift from theinitial “set” current I_(A) to the final “set” current I_(B) during the“set” operation, due to the change in resistance (R_(VR)) of thevariable resistance layer 206. One will note that the initial “set”current I_(A) will typically equal the minimum “set” current I_(MSC),which is discussed above.

Alternately, when a “reset” switching pulse 413 is delivered through astandard switching memory device, the memory device will switch from thelow-resistance-state (LRS) to the high-resistance-state (HRS), as shownby the arrow 431. One will note that the current flowing through theswitching memory device will shift from the initial “reset” currentI_(C) to the final “reset” current I_(D) during the “reset” operation,due to the change in resistance (RVR) of the variable resistance layer206.

Referring to FIG. 4B, the “sensing” pulse 412 may be applied to anappropriate set of the electrodes 102 and 118 during various“programming” operations, such as a “read” operation, to sense theresistance state of the resistive switching memory element 112 in thememory device. For example, the pulse 406 at a sensing voltage level,e.g., a “read” voltage level, V_(READ), such as about +0.5 volts (V) orother suitable voltage levels may be applied.

In one example, the resistive switching memory element 112 may initiallybe in a high resistance state (e.g., capable of storing a logic “zero”).The read-and-write circuitry 150, which is connected to the electrodes102 and 118, may apply a read voltage, V_(READ), to the resistiveswitching memory element 112 to sense the high resistance state ofresistive switching memory element 112, and the resulting “off” current(I_(OFF)) flowing through the resistive switching memory element 112 issensed.

The “set” switching pulse 411, which may be in opposite polarity of the“sensing” pulse 412, may then be applied to an appropriate portion ofthe electrodes 102 and 118 to place the resistive switching memoryelements 112 within these memory devices into its low-resistance state,when it is desired to store a logic “one” in a specified set of memorydevices. The read-and-write circuitry 150 may apply the pulse 401 at aset voltage level, V_(SET), which is often a negative voltage (e.g., anapplied voltage level in the range between −2 Volts and −4 Volts) acrossthe electrodes 102 and 118.

Depending on its past history, the resistive switching memory element112 can either be in an initial high resistance state or an initial lowresistance state. Thus, in one configuration, applying the “set”switching pulse 411 to the resistive switching memory element 112 causesit to switch to its low resistance state (e.g., the arrow 421 as shownin FIG. 4A). The change in the resistance state of resistive switchingmemory element 112 may be due to the redistribution or filling of traps(i.e., “trap-mediated”), or defects, in a resistive material layer withvariable resistance (e.g., the variable resistance layer 206 in FIGS. 2Aand 2B), when the device is reverse biased.

The defects or traps are commonly formed during the deposition, initialburn-in, or forming of the variable resistance layer 206, and thesedefects or traps are often created by a non-stoichiometric materialcomposition found in the formed variable resistance layer 206. V_(SET)and V_(RESET) are generally referred to as “switching voltages” herein.In turn, the overall resistance of the resistive switching memoryelement 112 determines what digital data is being stored by the memorydevice.

During a “write” operation, the state of the resistive switching memoryelement 112 can be changed into a desired state by applying varioussuitable write signals (e.g., biasing the read-and-write circuitry 150with desired currents, voltages, etc.) to an appropriate set of theelectrodes 102 and 118 of the memory device. Initially, a low resistancestate of the resistive switching memory element 112 can first be sensedusing the read and write circuitry 150 by applying the “sensing” pulse412 (e.g., the pulse 404 at the “read” voltage level, V_(READ)) to theresistive switching memory element 112, the read-and-write circuitry 150may sense the relatively high “on” current value (I_(ON)), indicatingthat the resistive switching memory element 112 is in its low resistancestate.

The “reset” switching pulse 413, which is usually in the same polarityas the “sensing” pulse 412, may then be applied to an appropriateportion of the electrodes 102 and 118 to place the resistive switchingmemory element 112 within the these memory devices into high-resistancestate, when it is desired to store a logic “zero” in a specified set ofthe memory devices.

The read-and-write circuitry 150 may apply the “reset” switching pulse413 (e.g., the pulse 405 at a set voltage level, V_(RESET)) which isoften a positive voltage (e.g., an applied voltage level in the rangebetween +2 Volts and +5 Volts) across the electrodes 102 and 118 toreset the resistive switching memory element 112 to its high resistancestate (e.g., the arrow 431 as shown in FIG. 4A). When the “reset”switching pulse 413 at the reset voltage level, V_(RESET), is removed,the resistive switching memory element 112 can once again becharacterized as in its high resistance state when another “sensing”pulse at the read voltage level, V_(READ) (e.g., the pulse 406) isapplied.

Accordingly, a plurality of the voltage pulses 401, 402, 403, 404, 405,406, 411, 412, 413 can be applied for a period of time to switch andsense the resistance states of the resistive switching memory element112 in the programming of the memory device. For example, a square ortrapezoidal shaped pulse for a period of about 1 μs to about 1 ns can beused to switch the resistive switching memory element 112.

In some embodiments, it may be desirable to adjust the length of eachpulse, depending on the amount of time needed to switch the resistiveswitching memory element 112. In one example, the “set” and “reset”pulses are each about 10 ns in length. Although the discussion of theresistive switching memory element 112 herein primarily provides bipolarswitching examples, some embodiments of the resistive switching memoryelement 112 may use unipolar switching, where the set and reset voltageshave the same polarity, without deviating from the scope of theinvention described herein.

To provide a measurable difference between the logic “zero” and logic“one” states, it is common to form the variable resistance layer 206 andother components of the resistive switching memory element 112 so thatthe difference between the I_(ON) and I_(OFF) currents have a differenceof at least one order of magnitude, for example, a current ratioI_(ON)/I_(OFF) of about 5 or above. In other words, the ratio of theelectrical resistances of the variable resistance layer 206 is decreasedby at least 5 times when switching between the high and the lowresistance states.

In operation of a conventional memory device, a “set” switching pulse,such as the pulse 401 as shown in FIG. 4B, is delivered through theconventional memory device to set a low resistance state or logic “one”state. In this case, a set voltage V_(SET) is applied across theelectrodes of the conventional memory device, which creates a first“set” current, I₁, to flow through the conventional memory device, dueto the impedance of the electrical components found in the memoryelement.

The first “set” current, I_(SET) or I₁ is equal to the applied “set”voltage V_(SET) divided by the sum of the impedances of a top electrodelayer (TEL), a variable resistance layer (VR), an optional intermediateelectrode (TEL), a current steering element (CSE), and a bottomelectrode layer (BEL) within the memory device. Therefore, in oneexample, the first “set” current I₁ is measured as:

I _(SET) =I ₁ =V _(SET)/(R _(TEL) +R _(VR) +R _(IEL) +R _(CSE) +R_(BEL))

It was found that the first “set” current I₁ in a conventional memorydevice may vary during the time that the “set” switching pulse isinitially applied across the electrodes 102 and 118. The first “set”current I₁ may have a low current region 409 that is created due to theelectrical properties of the material as it switches from the HRS to theLRS, and also have a final “set” switching region 411, where a final“set” current, I_(B), can flow through the conventional memory device.

Because the actual impedance of various electrode layers is generallysmall, due to the need to reduce the power loss in the device, and theimpedance of a variable resistance layer is desirably low to achieve alogic “one” state, the impedance of the current steering elementgenerally dominates the circuit of conventional memory devices (e.g.,R_(CSE)>>R_(TEL)+R_(IEL)+R_(BEL)+R_(VR)) and the impedance of thecircuit in this state equals approximately to the impedance of thecurrent steering element (R_(CSE)).

I _(SET) =I ₁ =˜I _(B) =˜V _(SET) /R _(CSE)

It was found that the resistances of the circuit in a conventionalmemory device at switching voltages are actually measured to be lowerthan expected. This is a problem because the magnitude of the setcurrent I₁ created by the pulse 401 became very close to I_(MAX), orload current I_(L), for such conventional memory devices, where I_(MAX)or I_(L) equals approximately to the set voltage divided by theimpedance of the current steering element:

I ₁ =I _(MAX) =I _(L) =˜V _(SET) /R _(CSE)

One will note that the difference between the “set” current I₁ and theminimum I_(MSC) current is much larger than necessary to cause thedevice to reliably switch to the logic “one” state. However, in practiceit has been found that the high currents delivered through conventionalmemory devices can permanently damage the memory element components andcause cross-talk to occur between adjacently connected devices.

Thus, the magnitude of the “set” current, I_(SET) or I₁, is particularlyimportant for bipolar switching applications that require a currentsteering element to be reverse biased to “set” the resistance of thememory element into a low resistance state. The act of driving a highcurrent through the current steering element 216, in a non-forwarddirection, can breakdown, generate heat within and ultimately damage thematerial layers used to form the current steering element and theresistive switching memory element, thus reducing the effective lifetimeof the current steering element and/or the resistive switching memoryelement.

It has been found that because the current steering element provides theprimary voltage drop in the memory device during the “set” operations(e.g., switch to “on” state), the current steering element often isrequired to operate near its breakdown voltage to reliably cause thevariable resistance layer to switch.

The application of the current steering element in this regime causesits impedance to drop over time due to damage to the material layers inthe current steering element. Typically the resistance (R_(CSE)) of anundamaged reverse biased diode type current steering element, forexample, may be in a range between about 1 and about 100 MΩ, whereas theresistance of a forward biased diode type current steering element maybe between about 1 and about 20 kΩ.

Therefore, after performing the “set” operation by applying the “set”switching pulse 411, it is common to apply a “sensing” pulse 412 toassure that the logic “one” state has been achieved. The application ofa sensing pulse 412, such as sensing pulse 404 in FIG. 4B, is generallyperformed by applying a V_(READ) voltage (e.g., +0.5V) across theelectrodes. If the “set” operation was performed correctly, the currentthrough a memory device during this sensing step equals the I_(ON)current, which equals the V_(READ) voltage divided by the impedance ofthe circuit (I_(ON)=V_(READ)/R_(TOTAL)). For a memory device that hasthe variable resistance layer in a low resistance state, the I_(ON)current will approximately equal to the V_(READ) voltage divided by theimpedance of the current steering element.

I _(ON) =˜V _(READ) /R _(CSE)

Next, in cases where it desirable to change the resistive switchingmemory element 112 from a low resistance state (i.e., logic “one” state)to a high resistance state (i.e., logic “zero” state), a “reset”switching pulse 413, such as the reset switching pulse 405 in FIG. 4B,is delivered through a memory device.

One will note that the largest current that is delivered through theswitching memory device during the “reset” operation will be achievedwhen the initial “reset” current I_(C) flows through the device. Thecurrent flowing through the device during the “reset” operation willthen tend to drop as the variable resistive layer 206 switches from aLRS to a HRS (e.g., the arrow 431 as shown in FIG. 4A).

Therefore, the pulse 413, which is schematically illustrated in FIG. 4B,will generally have high current portion 419 at the start of thedelivered pulse 413 and a stable region that equals the “reset” currentI₄ during the later stages of the “reset” operation. Therefore, the“reset” current I₄ achieved during the “reset” switching pulse 413 willgenerally equal the final “reset” current I_(D) and the maximum currentachieved during the pulse 413 will equal the initial “reset” currentI_(C).

It has been found that the magnitude of the current required to switch aresistive switching memory element from a low resistance state to a highresistance state is dependent on the magnitude of the current used to“set” the device in the low resistance state. If a high “set” current,such as current I₁, is delivered to the resistive switching memoryelement, then a higher “reset” current is required to achieve adesirable high resistance state.

Stated another way, the difference between the initial “reset” currentI_(C), and/or the final “reset” current I_(D), and the minimum “reset”current I_(MRC) current (I_(C)>I_(D)>I_(MRC)) needs to be larger thannecessary to cause the device to switch from the “on” to the “off” stateif the magnitude of the prior applied “set” current is too far from theminimum “set” current I_(MSC) (I_(SET)=I₁>>I_(MSC)). The larger thannecessary swings in the current used to switch between the “on” and“off” states can damage the materials and components in the switchingmemory device, thus affecting the memory element's lifetime andreliability.

Next, after delivering the “reset” switching pulse 413, it is common toapply a “sensing” pulse 412, such as the sensing pulse 406 in FIG. 4B,to assure that the logic “zero” state has been achieved. The sensingpulse 412 is generally performed by applying a V_(READ) voltage (e.g.,+0.5V) across the electrodes.

If a “reset” operation was performed correctly, the current through amemory device during this sensing step will equal the I_(OFF) current,which equals to the V_(READ) voltage divided by the sum of the impedanceresistance of the current steering element (R_(CSE)) and the impedanceresistance of the variable resistance layer (R_(VR)). Therefore, in oneexample, the I_(OFF) current for a memory device will be as follows.

I _(OFF) =˜V _(READ)/(R _(CSD) R _(VR))

Integrating a Current-Limiting Layer and a Current-Reducing Layer in anImproved Memory Device

As discussed above, embodiments of the invention integrate andincorporate at least one current-limiting layer 220 and at least onecurrent-reducing layer 230 in a memory device, such as the memory device200 as described in FIGS. 1, 2A-2C, 3A-3D, for limiting and/orminimizing the current spikes during sensing and programming the logicstates for each of the interconnected memory devices 200 as well asreducing the magnitude of the current flowing through the interconnectedmemory devices 200 during device operation. Within the memory device200, the MIM stack of the resistive switching memory element 112 offersbistable resistance (e.g., LRS and HRS).

Referring back to FIG. 2C, when the read-and-write circuitry 150 appliesa “set” pulse (e.g., the “set” switching pulse 411 or the pulse 403 asshown in FIG. 4B) at a “set” voltage level, V_(SET), across theelectrodes 102, 118 to “set” the memory device 200 into a low resistancestate (L_(RS)) or logic “one” state, a “set” current, I_(SET)** (or I₃,as shown in FIG. 4B), is thus created. The “set” current, I_(SET)** orI₃, flowing through the memory device 200 during this “set” operationequals the V_(SET) voltage divided by the sum of all impedances withinthe memory device 200. Therefore, in one example, as shown in FIG. 2C,the set current, I_(SET)** or I₃, equals the following:

I _(SET) **=I ₃ =V _(SET)/(R ₆ +R ₅ +R ₄ +R ₃ +R ₂ +R ₁ +R _(IEL))

Because the impedance of the electrodes are generally small, due to theneed to reduce the power loss in the memory device, and the impedance ofthe variable resistance layer 206 is desirably low to achieve a logic“one” state, the impedances of the current steering element 216, thecurrent-limiting layer 220, and the current-reducing layer 230 willdominate the circuit (e.g., (R₄+R₃+R₂)>>R₁+R_(IEL)+R₅+R₆) and theimpedance of the circuit in this logic “one” state (I_(CIRCUIT)**=I₃) iseffectively equal to the sum of the impedances of the current steeringelement 216, the current-limiting layer 220, and the current-reducinglayer 230 (i.e., R₄+R₃+R₂).

I _(SET) **=˜V _(SET)/(R ₄ +R ₃ +R ₂)

Accordingly, the magnitude of the “set” current, I_(SET)**, is equal tothe maximum current I_(MAX)** for the memory device 200 near the end ofthe “set” switching pulse 411. Because of the presence of the addedimpedance of the current-reducing layer 230 (R₄) and thecurrent-limiting layer 220 (R₃) in the memory device 200 (as compared toconventional memory devices), the maximum current, I_(MAX)**(I_(MAX)**=I_(SET)**=I₃) is thus smaller than I₁=I_(MAX)=I_(L), which asdiscussed above, is the maximum current that can flow through aconventional memory device without damaging the memory device. It shouldbe noted that in a conventional memory device, the current steeringelement 216 typically provides the only impedance to current flow duringthis “set” operation.

I _(SET) **=I ₃ =I _(MAX) **<I ₁ =I _(MAX) =I _(L) =˜V _(SET) /R _(CSE)

In general, it is desirable to form the current-limiting layer 220 andthe current-reducing layer 230 so that their resistance (e.g., R₃ andR₄) limit the current flowing through the resistive switching memoryelement 112 to a value (e.g., the current I₂ as shown in FIG. 4B) thatis just greater the minimum “set” current, I_(MSC)**, of the memorydevice 200, as illustrated by the pulse 402, and still allow the logic“one” state to be reliably “set” by the applied V_(sEr) voltage.

I₂=I_(MAX)** and I₂ is designed to be close to I_(MSC)**

I _(MSC) **<I ₂ =I _(MAX) **<<I _(MAX) =I ₁

Incorporating the current-limiting layer 220 and the current-reducinglayer 230 into the memory device 200 to function together with theresistive switching memory element 112 can help reduce the apparentminimum I_(MSC) current required to cause the variable resistance layer206 to change to a low resistance state, because the addition of theresistances of the current-reducing layer 230 (R₄) and thecurrent-limiting layer 220 (R₃) in the circuit will reduce the swing incurrent required to “set” and “reset” the variable resistance layer 206at the same fixed applied voltage.

The reduction in the programming currents will thus affect the densityand movement of the traps in the variable resistance layer 206 of theresistive switching memory element 112. Not intending to be bound bytheory, but it is believed that when a smaller “on” state switchingcurrent is applied to a memory device, the formed filament(s) or alignedtraps in the variable resistance layer will be smaller in size than if ahigher “on” current is applied, thus making the filament(s) easier toalter during the “reset” phase of the resistive switching process.

The maximum current per unit area through the current-limiting layer 220and the current-reducing layer 230 can be approximated byI_(MAX)**=nqvs, where n is the free carrier density through the layers,q is the charge of an electron, and vs is the saturation velocity of theelectrons.

In one embodiment, the magnitude of the maximum current, I_(MAX)**,through the memory device 200 is adjusted by the selection of theresistivity (ρ) and the thickness (L) of the current-limiting layer 220and the current-reducing layer 230 in relation to the size of the memorydevice 200. For example, the current may be adjusted by defining thethickness of the current-limiting layer 220 and the current-reducinglayer 230.

As an example, for a memory device 200 with 15 nm×15 nm area, acurrent-limiting layer 220 having a thickness (L) of about 5 angstromsto 200 angstroms and a resistivity of between about 1 Ω-cm and about 10Ω-cm and the current-reducing layer 230 having a thickness of about 5angstroms to 50 angstroms are sufficient to provide the necessaryresistance to control the current flowing through the memory device 200.

As the size of the memory device 200 increases, the resistivity (ρ) andthickness (L) of the current-limiting layer 220 and the current-reducinglayer 230 may need to be increased as well. Conversely as the size ofthe memory device 200 decreases, the resistivity and/or thickness of thecurrent-limiting layer 220 and the current-reducing layer 230 may needto be reduced. Most likely, to reduce the aspect ratio of the overallmaterial stack within a memory device, the thickness of the materiallayers within the resistor structure 220 can be advantageously reduced.

In operation of the memory device 200, a sensing pulse, such as the“sensing” pulse 412 (e.g., the pulse 404 in FIG. 4B), can be applied tothe electrodes 102, 118 after performing the “set” operation to thememory device 200 and the logic “one” state has been achieved. If the“set” operation was performed correctly, the current through the memorydevice 200 during this sensing step equals the I_(ON)** current, whichequals the V_(READ) voltage divided by the impedance of the circuit(I_(ON)**=V_(READ)/R_(TOTAL), whereR_(TOTAL)=R₆+R₅+R₄+R₃+R₂+R₁+R_(IEL)).

When the variable resistance layer 206 is in a low resistance state, theI_(ON)** current of the memory device 200 approximately equals theV_(READ) voltage divided by the impedances of the current steeringelement 216, the current-limiting layer 220, and the current-reducinglayer 230.

I _(ON) **=˜V _(READ)/(R ₂ +R ₃ +R ₄)

The “reset” switching pulse 413, such as the “reset” switching pulse 405as shown in FIG. 4B, can be delivered through the memory device 200,when it is desirable to change the resistive switching memory element112 from a low resistance state (i.e., logic “one” state) to a highresistance state (i.e., logic “zero” state). In a conventional device,the difference between the “reset” current I₄ and the minimum “reset”current I_(MRC) current needs to be larger (I₄>I_(MRC)) than necessaryto cause the conventional memory device to reliably switch from the “on”to the “off” state.

As noted above, because the current steering element in a conventionalmemory devices is the primary voltage drop during “set” operations(e.g., switch to “on” state), conventional current steering elements areoften required to operate near the breakdown voltage to reliably causethe variable resistance layer to switch, which is not the case in thememory device 200 due to the added voltage drop provided by thecurrent-limiting layer 220 and the current-reducing layer 230. By addingthe current-limiting layer 220 and the current-reducing layer 230, the“reset” current I_(RESET)** for the memory device 200 equals thefollowing:

I _(RESET) **=I ₄ =˜V _(RESET)/(R _(CSE)+R₂₂₀ +R ₂₃₀) or ˜V _(RESET)/(R₂ +R ₃ +R ₄)

Next, the “sensing” pulse 412, such as the pulse 406 in FIG. 4B, isoften applied to assure that the logic “zero” state has been achieved,after delivering the “reset” switching pulse 413. If a “reset” operationwas performed correctly, the current through the memory device 200during this sensing step equals the I_(OFF) current, which equals theV_(READ) voltage divided by the sum of the impedance (R₂) of the currentsteering element 216, the impedance (R₅) of the variable resistancelayer 206, and the impedance (R₃) of the current-limiting layer 220, andthe impedance (R₄) of the current-reducing layer 230. Therefore, in oneexample, the I_(OFF)** current for the memory device 200 is as follows.

I _(OFF) **=˜V _(READ)/(R ₂ +R ₃ +R ₄ +R ₅)

The integration of the current-limiting layer 220 and thecurrent-reducing layer 230 in the memory device 200 reduces the voltageapplied across the current steering element 216, and thus prevents thecurrent steering element 216 from being damaged due to the applicationof a voltage near the breakdown state of the material layers and/or thedegradation of the material layers over time due to damage created bythe repetitive application of the programming voltages.

One will note that, the actual impedance (R_(CSE)**) of the currentsteering element 216 is generally greater than the impedance of acurrent steering element disposed in conventional current steeringelements, because the added voltage drop of the current-limiting layer220 and the current-reducing layer 230 in the device circuit willprevent the current steering element 216 from being damaged by theapplication of the programming currents during normal operations.

In one example, the total resistance of the current-limiting layer 220and the current-reducing layer 230 is dependent on the thickness of thelayers, device area, and geometry and other device specificationrequirements, and can be, for example, between about 10 kΩ and about 600kΩ, such as between about 10 kΩ and about 200 kΩ. One will note that itis assumed that the contact resistances between the various layers inthe memory device 220, such as the contact resistance formed between theelectrode 102 and the variable resistance layer 206, are negligible tohelp reduce the complexity of the discussion of the circuit.

Whereas the current steering element 216 may include two or more layersof semiconductor material that are adapted to control the flow ofcurrent through the memory device 200, the resistance of each of thecomponents in the current steering element 216 are not individuallydiscussed herein to minimize the complexity of the discussion, and thusan overall current steering element resistance R_(CSE) or R₂, forexample, is used to represent the overall impedance of the currentsteering element 216.

Other examples of controlling the resistance values of the variousmaterial layers in the formed resistive switching element 112 and thelevels of current flowing through a memory device during resistiveswitching operations are found in a co-pending U.S. patent applicationSer. No. 13/228,744, filed Sep. 9, 2011, and a continuation-in-part ofco-pending U.S. patent application Ser. No. 13/353,000, filed Jan. 18,2012, which claims benefit of U.S. provisional patent application Ser.No. 61/513,355, filed Jul. 29, 2011. The disclosure materials of theseco-pending patent applications are hereby incorporated by reference inits entirety.

FIGS. 5A-5C demonstrated the results of the measured switching currentlevels among exemplary formed memory devices 200. In operation, “set”and “reset” programming operations are performed by cyclically applying“set” and “reset” switching pulses to a memory device 200. After each ofthe “set” and “reset” switching pulses are applied, a “sensing” pulse ata V_(READ) voltage is generally used to assure that appropriate devicelogic “one” or “zero” states have been achieved and the current flowingthrough the memory device 200 at each sensing step would be close orequal to “I_(ON)” or “I_(OFF),” after each of the “set” or “reset”switching pulse, respectively.

In FIG. 5A, the measured currents of a conventional memory device during“set” and “reset” switching operations are plotted against the numbersof switching cycles, where each switching cycle represents cyclicallyapplying a set pulse, a sensing pulse, a reset pulse, and anothersensing pulse to the memory device. As illustrated in FIG. 5A, eachsolid black dot (e.g., sense current level 510) represents the currentlevel measured by applying a “sensing” pulse (e.g., V_(READ)) after each“set” switching pulse has been applied to the conventional memorydevice.

Each sense current level 540A, which is represented by a hatched dot, isthe sense current level measured by applying a “sensing” pulse aftereach “reset” switching pulse has been applied to the conventional memorydevice. As shown in FIG. 5A, the sense current levels 540A are close tothe desired I_(OFF) levels.

However, as shown in FIG. 5A, it is observed that the measured sensingcurrent levels at V_(READ) after performing each “set” operation in aconventional memory device, as represented by the sense current levels510, are considerably higher than needed (e.g., much higher than thedesired I_(ON) levels as shown in FIG. 5A).

For example, in a conventional memory device, the sense current levels510 measured after each device “set” operation vary to a large extentamong themselves and, as measured, include sense current levels 502A andsense current levels 504A. In general, the high sensing currents createdby a high current delivered during “set” operations completed in aconventional memory device, as shown by the sense current levels 502Aand the sense current levels 504A, will likely cause device failure tothe conventional memory device.

For example, the magnitudes of the sense current levels 502A are too faraway from the desired I_(ON) levels. What is worse is that, the “set”current levels of a conventional memory device may encounter a currentspike, which may be created by the large currents flowing through thememory device during electrical-forming or switching operations whenvoltage pulses at high voltage levers or longer pulsing times areapplied to the memory device.

Once such a high current spike level is reached in a conventional memorydevice, the “set” current level cannot be adjusted back. The magnitudesof such current spikes, as represented by the sense current levels 504A,often exceed the device compliance current level, I_(CC), and may damagethe memory device. In addition, the clustering of the sense currentlevels 504A indicates that, once a conventional memory device is formedand has encountered such extremely high current spikes during theswitching operations, there is no effective way to reduce the “set”current levels and the damage to the device may be permanent.

In FIG. 5B, in accordance with one embodiment of the invention, anonvolatile memory device having the current-limiting layer 220 isformed and the current levels of the nonvolatile memory device havingthe current-limiting layer 220 are measured. Each solid black dot (e.g.,sense current level 520) represents the current level measured byapplying a “sensing” pulse (e.g., V_(READ)) after each “set” switchingpulse has been applied to the memory device having the current-limitinglayer 220.

The sense current levels 520 include sense current levels 502B and sensecurrent levels 506. Each sense current level 540B, which is representedby a hatched dot, is the sense current level measured by applying a“sensing” pulse after each “reset” switching pulse has been applied tothe memory device having the current-limiting layer 220.

The current levels (e.g., the sense current levels 540B in FIG. 5B)measured in the memory device having the current-limiting layer 220after performing each “reset” operation are substantially the same asthe current levels measured in a conventional memory device (e.g., thesense current levels 540A in FIG. 5A), because the current level at adevice “Off” state is approaching its intrinsic leakage current.

As shown in FIG. 5B, the presence of the current-limiting layer 220 inthe memory device limits the occurrences of high current spikes during“set” switching operations. For example, in FIG. 5B, the current levelsin the memory device having the current-limiting layer 220 afterperforming each “set” operation are measured to the reduced levels(e.g., the sense current levels 506), as indicated by a shift from theblank dots at the high current spikes levels (e.g., the blank dots insense current levels 504B in FIG. 5B, which correspond to the currentspikes of the sense current levels 504A shown in FIG. 5A as discussedabove) to the low current levels (e.g., the sense current levels 506 asshown in FIG. 5B) measured after performing each “set” operation.

However, in FIG. 5B, some portions (e.g., the sense current levels 502B)of the sense current levels 520 in the memory device having thecurrent-limiting layer 220 after performing each “set” operation aremeasured to the same levels as the current levels measured in theconventional memory device (e.g., the sense current levels 502A in FIG.5A), and thus, still having the same problem of being too far away fromthe desired I_(ON) levels and likely causing device failure. Therefore,there is still a need to reduce the overall high magnitude of currentsduring “set” operations.

In FIG. 5C, to further solve the high current problems during the “set”operations, in accordance with one or more embodiments of the invention,a nonvolatile memory device, such as the memory device 200 having thecurrent-limiting layer 220 and the current-reducing layer 230, isformed. In FIG. 5C, the Y-axis represents the sense current levelsobtained by cyclically applying a set pulse, a sensing pulse, a resetpulse, and another sensing pulse to the memory device 200 having thecurrent-limiting layer 220 and the current-reducing layer 230 disposedtherein. The X-axis represents the numbers of switching cycles.

Each solid black dot (e.g., sense current levels 530) represents thecurrent levels measured by applying a “sensing” pulse (e.g., V_(READ))after each “set” switching pulse has been applied to the memory device200 having the current-limiting layer 220 and the current-reducing layer230. The sense current levels 530 include sense current levels 508 andmeasured sense current levels 509.

Hatched dots (e.g., sense current levels 540C in FIG. 5C) represent thecurrent levels measured by applying a “sensing” pulse after each “reset”switching pulse has been applied to the memory device 200 having thecurrent-limiting layer 220 and the current-reducing layer 230. The sensecurrent levels 540C measured in the memory device 200 in FIG. 5C aresubstantially the same as the sense current levels 540A in FIG. 5A, asthe current level is reaching its intrinsic leakage current level atdevice “Off” state.

As shown in FIG. 5C, in accordance with one or more embodiments of theinvention, the presence of the current-reducing layer 230 is compatiblewith the incorporation of the additional current-limiting layer 220, andtogether, the current-limiting layer 220 and the current-reducing layer230 can effectively function to further reduce the current levelsflowing through the memory device 200 and limit the damage to the formedmemory device 200 due to the current spikes flowing through the circuitelements.

For example, in FIG. 5C, the currents that flow through the memorydevice 200 having the current-limiting layer 220 and thecurrent-reducing layer 230 after performing “set” switching operationsare measured to the reduced levels (e.g., the sense current levels 508,509), as indicated by a shift from the blank dots at the high currentlevels (e.g., sense current levels 502C, 504C, which correspond to thesense current levels 502A, 504A shown in FIG. 5A as discussed above) tothe current levels (e.g., the sense current levels 508, 509 as shown inFIG. 5C) measured after performing the “set” operations in the memorydevice 200 having both the current-limiting layer 220 and thecurrent-reducing layer 230.

EXAMPLES

In accordance with one or more embodiments of the invention, a processof forming the memory device 200 includes forming a resistive switchingmemory element 112 having an intermediate electrode layer 210 comprisingan n-doped polysilicon layer, a variable resistance layer 206 that isabout 50 angstroms thick and comprises hafnium oxide (Hf_(x)O_(y)), acurrent-reducing layer 230 that comprises aluminum doped hafnium oxide(doped Hf_(x)O_(y)) at a thickness of between about 5 angstroms thickabout 20 angstroms thick with a resistivity of about 2 Ω-cm and acurrent-limiting layer 220 that comprises hafnium nitride (Hf_(x)N_(y))at a thickness of between about 50 angstroms and 200 angstroms with aresistivity of between about 10 Ω-cm and an electrode 102 that comprisesa layer of titanium nitride (TiN). After forming the memory device 200,optionally at least one thermal processing step is performed to activatethe materials within layers and enhance adhesion between the layers.

In another example of a memory device 200, the resistive switchingmemory element 112 comprises: an intermediate electrode 210 comprisingan n-doped polysilicon layer, a current-reducing layer 230 thatcomprises silicon oxide at a thickness of about 15 angstroms with aresistivity of about 1.5 Ω-cm and a variable resistance layer 206 thatis about 50 angstroms thick and comprises hafnium oxide (Hf_(x)O_(y)),and an electrode 102B that comprises a layer of titanium nitride (TiN).

After the resistive switching memory element 112 is formed, acurrent-limiting layer 220 that comprises between about 5 angstroms and200 angstroms of silicon nitride (Si_(x)N_(y)) with a resistivity ofabout 5 Ω-cm, and an electrode 102A that comprises a layer of n-dopedpolysilicon layer are deposited. After forming the memory device 200,then at least one thermal processing step is performed.

In yet another example of a memory device 200, a resistive switchingmemory element 112 is formed that comprises: an intermediate electrode210 comprising an n-doped polysilicon layer, a current-reducing layer230 that comprises about 50 angstroms of silicon oxide with aresistivity of about 2 Ω-cm a variable resistance layer 206 that isabout 50 angstroms thick and comprises hafnium oxide (Hf_(x)O_(y)), acurrent-limiting layer 220 that comprises between about 50 angstroms and1000 angstroms of a silicon layer that is doped to a level of betweenabout 10¹³ and about 10¹⁶ atoms/cm³, and an electrode 102 that comprisesa layer of titanium nitride (TiN).

In one example, the current-limiting layer 220 comprises an n-typesilicon layer that has a boron doping level of about 10¹³ to about 10¹⁶atoms/cm³. In another example, the current-limiting layer 220 comprisesa p-type silicon layer that has a phosphorous doping level of about 10¹³to about 10¹⁶ atoms/cm³. After forming the memory device 200, then atleast one thermal processing step is performed.

In another example of a memory device 200, a resistive switching memoryelement 112 is formed that comprises: an intermediate electrode 210comprising an n-doped polysilicon layer, a current-reducing layer 230that is about 50 angstroms thick and comprises silicon oxide, a variableresistance layer 206 that is about 50 angstroms thick and compriseshafnium oxide (Hf_(x)O_(y)), a current-limiting layer 220 that isbetween about 50 angstroms and 500 angstroms thick and comprisestitanium nitride (Ti_(x)N_(y)), and an electrode 102 that comprises alayer of titanium nitride (TiN). After forming the memory device 200,then at least one thermal processing step is performed.

In another example of a process of forming the memory device 200, aresistive switching memory element 112 is formed that comprises: anintermediate electrode 210 comprising an n-doped polysilicon layer, acurrent-reducing layer 230 that is about 50 angstroms thick andcomprises silicon oxide, a variable resistance layer 206 that is about50 angstroms thick and comprises hafnium oxide (Hf_(x)O_(y)), acurrent-limiting layer 220 that is between about 50 angstroms and 500angstroms thick and comprises a stoichiometric tantalum nitride (TaN),layer and an electrode 102 that comprises a layer of titanium nitride(TiN). After forming the memory device 200, then at least one thermalprocessing step is performed.

Exemplary deposition process for depositing the current-limiting layer220 over the surface of the variable resistance layer 206, theintermediate electrode layer 210, the electrode 102B, the electrode102B, the electrode 118B, or the electrode 118A include PVD, CVD, ALD orother similar process. In one embodiment, the current-limiting layer 220is a metal nitride layer (e.g., Hf_(x)N_(y), Ta_(x)N_(y)), a metal oxidelayer (e.g., Al₂O₃, ZrO₂), or semiconductor layer (e.g., doped Si,Si_(x)N_(y)) that is formed by use of a PVD, CVD or ALD process.

In one example, the current-limiting layer 220 may be formed to athickness between about 50 angstroms and about 500 angstroms, andcomprise a material such as Ta, Ti, Hf, or Si. In one example, thecurrent-limiting layer 220 is formed using a PVD process that deposits aHf_(x)N_(y) layer at a deposition rate of between about 4 to 8angstroms/minute using a pure hafnium target and maintaining theprocessing environment during the PVD deposition process to betweenabout 1% and about 40% nitrogen (N₂) and the balance being argon (Ar)gas.

It has been found that maintaining the nitrogen concentration in a PVDprocessing environment to a range between 10-15% nitrogen will create alayer that is highly resistive (e.g., 103 to 105 μΩ-cm), and maintainingthe nitrogen concentration in a PVD processing environment to aconcentration of greater than about 40% will form a dielectric layer.Therefore, one can adjust the layer thickness and resistivity to form ahafnium nitride layer containing the current-limiting layer 220 that hasa desirable resistance.

In one process example, the nitrogen concentration in the processingenvironment during deposition is controlled to form a hafnium nitride(HfN) layer that has a desirable resistivity within a range of about 1μΩ-cm to about 500 μΩ-cm.

In another example of a process of forming the current-limiting layer220, an ALD process using a tert-butylimido tris-diethylamido tantalum(TBTDET) or pentakis(dimethylamino)tantalum PDMAT precursor and ammonia(NH3) at a temperature of about 150° C. to about 300° C. is used to forma TaN film of about 50 angstroms to about 500 angstroms thick. In oneprocess example, the tantalum (Ta) to nitrogen (N) concentration ismaintained at a ratio of about 1:1 to achieve a layer that has aresistivity of between about 1000 μΩ-cm and about 5000 μΩ-cm.

In another example of a process of forming the current-limiting layer220, an ALD process using a tetrakis(dimethylamino) titanium (TDMAT)precursor and ammonia (NH₃) at a temperature of about 100° C. to about300° C. is used to form a TiN film that is between about 50 angstromsand about 500 angstroms thick. In one process example, the titanium (Ti)to nitrogen (N) concentration is maintained at a ratio of about 1:1 toachieve a layer that has a resistivity of between about 1000 and about5000 μΩ-cm.

In yet another example of a process of forming the current-limitinglayer 220, an ALD process using a tetrakis(dimethlyamino) hafnium(TDMAH) precursor and ammonia (NH3) at a temperature of about 150° C. toabout 300° C. is used to form a HfN film of about 50 angstroms to about500 angstroms thick. It has been found that by maintaining the hafnium(Hf) to nitrogen (N) concentration during deposition at a ratio of about1:1.3 a resistive switching having desirable switching properties can beachieved.

In yet another example of a process of forming the current-limitinglayer 220, an ALD process using a tetrakis(dimethlyamino) zirconium(TDMAZ) precursor and ammonia (NH3) at a temperature of about 150° C. toabout 300° C. is used to form a ZrN film of about 50 angstroms to about500 angstroms thick. It has been found that by maintaining the zirconuim(Zr) to nitrogen (N) concentration during deposition at a ratio of about1:1.3 a resistive switching having desirable switching properties can beachieved.

Exemplary deposition process for depositing the current-reducing layer230 over the surface of the variable resistance layer 206, theintermediate electrode layer 210, or the electrode 118B, or theelectrode 118A include PVD, CVD, ALD, other plasma treatment processtechniques, and/or chemical treatment solutions. In one example, thecurrent-reducing layer 230 may be a metal oxide, such as zirconium oxide(ZrxOy) or aluminum oxide (Al_(x)O_(y)).

The current-reducing layer 230 can be comprised of a material that has agreater band gap than that of the variable resistance layer 206. Forinstance, if the variable resistance layer 206 is HfO₂ with a band gapof approximately 5.7 eV, the current-reducing layer 230 may be chosen tobe Al₂O₃ with a band gap of approximately 8.4 eV.

For example, the current-reducing layer 230 can be fabricated on thesurface of the intermediate electrode layer 210 where a native oxidelayer was removed and an ALD deposition process is used to depositconformal layers with atomic scale thickness control.

For depositing a metal oxide (e.g., Al₂O₃, ZrO₂), ALD is a multistepself-limiting process that includes the use of two reagents: a metalprecursor (e.g., trimethylaluminum (TMA),tetrakisethylmethylaminozirconium (TEMEZr)) and an oxidizer (e.g.,oxygen, ozone, water). The metal precursor is first introduced into aprocessing chamber containing the substrate 201 having the intermediateelectrode layer 210 and adsorbs on the surface of the intermediateelectrode layer 210.

Next, the oxidizer is introduced into the chamber and reacts with theadsorbed layer to form a deposited metal oxide layer. The process isrepeated to form a number of successive layers that make up thecompleted current-reducing layer 230. The current-reducing layer 230 maybe fabricated to a thickness between about 3 angstroms and about 10angstroms. The processes may be performed at atmospheric or vacuumconditions at between about 200° C. and about 300° C.

The current-reducing layer 230 increases the barrier height at theinterface between the electrodes 102, 118 and the variable resistancelayer 206. The increased barrier height reduces the magnitude of thecurrent that flows through the memory device 200 due to increased energyrequired to move the carrier over or tunnel through the fabricatedbarrier so that the current is able to flow through the memory device200, resulting in desirably lower switching current for the memorydevice 200.

In another example, the current-reducing layer 230 may be a doped metaloxide layer fabricated on the surface of the electrode 118, 118B, theintermediate electrode layer 210, or the variable resistance layer 206using a deposition process, such as ALD, PEALD, CVD, PECVD, PVD, or thelike.

For example, the current-reducing layer 230 may be formed into a portionof the variable resistance layer 206 deposited over the surface of thesubstrate 201 using a PVD, CVD or ALD deposition process. The variableresistance layer 206 may comprise a metal oxide layer, such asHf_(x)O_(y), Ta_(x)O_(y), Al_(x)O_(y), La_(x)O_(y), Y_(x)O_(y),DY_(x)O_(y), Yb_(x)O_(y) and/or Zr_(x)O_(y), formed to a thickness ofbetween about 20 angstroms and about 100 angstroms, such as betweenabout 30 angstroms and about 50 angstroms. The variable resistance layer206 can be deposited using any desired technique, but in someembodiments described herein is deposited using an ALD process.

In one example, an ALD process using tetrakis(dimethylamino)hafnium(TDMAH) and an oxygen containing precursor (e.g., water vapor) at atemperature of about 250° C. is used to form a 30 angstroms thickhafnium oxide (Hf_(x)O_(y)) which acts as the variable resistance layer206 and a dopant, such as aluminum or zirconium is delivered in to theALD process chamber prior to or after the desired thickness of thevariable resistance layer 206 is obtained to additionally form a layerof aluminum (Al) or zirconium (Zr) doped hafnium oxide(Hf_(x)O_(y))-containing current reducing layer 230.

In still another example, the current-reducing layer 230 is a layer ofhigh-k material fabricated on the surface of an electrode (e.g., theelectrode 118, 118B, or the intermediate electrode layer 210) prior tofabricating the variable resistance layer 206. Examples of suitablehigh-k materials include aluminum oxide (Al₂O₃), zirconium oxide (ZrO₂),yttrium oxide (Y₂O₃), silicon nitride (Si₃N₄), silicon oxynitride(SiON), and the like.

The presence of the high-k interfacial current-reducing layer 230naturally forms a barrier height (qφ) at the intermediate electrode 210.The size of the barrier height (qφ) is strongly dependent on the bandgapof the material used to form the current-reducing layer 230.

Thus, providing a suitable high-k material at the current-reducing layer230 increases the barrier height (e.g., increase of 1 eV to 5 eVcompared to native silicon oxide) at the interface between theintermediate electrode 210 and the variable resistance layer 206 due tothe increased bandgap of the current-reducing layer 230, which lowersthe magnitude of current (e.g., I_(ON), I_(OFF)) that can flow throughthe device during operation, resulting in desirably lower switchingcurrent of the device 200. Providing a suitable high-k material as thecurrent-reducing layer 230 also reduces the equivalent oxide thickness(EOT) of the dielectric layer stack fabricated in the device 200,allowing thinner layers to be used which results in desirably lowerswitching current and voltage.

In still another example, the current-reducing layer 230 may be a nativeoxide or silicide layer formed between the variable resistance layer 206and an electrode (e.g., the electrodes 118, 102, 118B, 102B, or theintermediate electrode layer 210). The native oxide layer can be formedby cleaning the substrate surface with a substrate cleaning solution,such as a solution of hydrogen fluoride (HF) and deionized (DI) water.The cleaning solution may be an aqueous solution that contains betweenabout 0.1% and about 10% weight of hydrogen fluoride (HF) that ismaintained at a temperature between about 20° C. and about 30° C.

In yet another example, the current-reducing layer 230 is a layer ofhigh quality silicon oxide fabricated over the surface of the substrate201, such as over the surface of the variable resistance layer 206, theintermediate electrode layer 210, the electrode 102, the electrode 102B,the electrode 118B, or the electrode 118.

Optionally, the surface of the substrate is cleaned with a substratecleaning solution and the native oxide material is removed using abuffered oxide etch (BOE), such as a mixture of ammonium fluoride (NH₄F)and hydrofluoric acid (HF) prior to subjecting the substrate 201 with anozone treatment or nitridation treatment. The current-reducing layer 230is fabricated by intentionally fabricating a high quality silicon oxidelayer over the surface of the substrate 201.

In one embodiment, the silicon oxide layer is fabricated by performingan ozone treatment on a native oxide layer formed naturally over acleaned surface of the substrate 201. In another embodiment, the siliconoxide containing current-reducing layer is fabricated by performing anozone treatment on the surface of a material layer (e.g., the surface ofthe variable resistance layer 206, the intermediate electrode layer 210,the electrode 102, the electrode 102B, the electrode 118B, or theelectrode 118).

The ozone treatment provides a denser, higher quality layer of siliconoxide than a native silicon oxide layer naturally formed on the surfaceof the substrate 201, resulting in desirably lower switching current ofthe device 200. The ozone treatment may be a plasma process performed atbetween about 200° C. and about 300° C. Ozone may be flown into a plasmachamber at between about 500 sccm and about 1000 sccm from about 30seconds to about 10 minutes during the ozone treatment. The ozoneexposure may be continuous or pulsed.

In another embodiment, the current-reducing layer 230 is formed byperforming a nitridation process on the native oxide layer as a siliconoxynitride (SiON) material layer. In one example, a partially fabricatedmemory device 200 having a native oxide material layer on its surface isannealed in a nitrogen environment, such as NH₃, N₂O, NO, or the like.In this example, the partially fabricated memory device 200 is heated toa temperature between about 750° C. and about 900° C. at a pressure ofless than about 100 Torr for a time period between about 30 second andabout 120 seconds.

In another example, the SiON-containing current reducing layer 230 isformed by plasma nitridation of a native oxide layer. In this example,the partially formed memory device 200 is exposed to plasma comprising anitrogen source, such as nitrogen gas (N₂), NH₃, or combinationsthereof. The plasma may further include an inert gas, such as helium,argon, or combinations thereof. The pressure in the chamber during theplasma exposure may be between about 1 mTorr and about 30 mTorr, and thetemperature may be may be maintained at between about 200° C. and about500° C.

In another embodiment, the silicon oxide containing current-reducinglayer is fabricated by using chemical treatment. In this embodiment, achemical oxidation solution, such as a mixture of ammonium hydroxide(NH₄OH), hydrogen peroxide (H₂O₂), and de-ionized (DI) water (hereafter,the APX mixture) is used to chemically treat the surface of a materiallayer (e.g., the surface of the variable resistance layer 206, theintermediate electrode layer 210, the electrode 102, the electrode 102B,the electrode 118B, or the electrode 118) and form a thin layer of goodquality silicon oxide film.

The ratio of NH₄OH to H₂O₂ to DI water in the APX mixture may be fromabout 1:1:5 to about 1:1:50. For example, the surface of theintermediate electrode layer 210 may be exposed to the APX mixture at atemperature between about 25° C. and about 75° C. Following the chemicaloxidation treatment, the surface of the substrate 201 may be exposed toa dilute hydrochloric acid (HCl), such as 1:100 HCl to DI water.

The ozone treatment or chemical oxidation treatment provides a denser,higher quality layer of silicon oxide than the native silicon oxidenaturally formed over a surface of a cleaned substrate, resulting indesirably lower switching current of the device 200. In one embodiment,the above described nitridation process may be performed after the ozoneor chemical treatment.

Accordingly, the current-reducing layer 230 may be an intentionallyfabricated silicon oxide-containing layer designed to provide a numberof beneficial characteristics at the interface between the variableresistance layer 206 and an electrode (e.g., the electrodes 118, 102,118B, 102B, or the intermediate electrode layer 210) as compared to anative oxide layer formed naturally after cleaning a surface of asilicon-containing material layer.

The current-reducing layer 230 also provides additional benefits, suchas passivation at the surface of an electrode. In a conventionallyfabricated memory device, the interface region formed between theelectrodes and the variable resistance layer 206 generally contains manydefects that can increase carrier recombination and prevent a goodelectrical contact from being formed between these fabricated adjacentlayers.

In general, the amount of carrier recombination is a function of howmany dangling bonds (i.e., unterminated chemical bonds) are present atthe interface. These unterminated chemical bonds act as defect traps,which can act as sites for carrier recombination and increase theresistance to the flow of the “on” and “off” currents through thefabricated device, resulting in the high sense current levels 510, asshown in FIG. 5A.

Therefore, in one embodiment of the invention, a passivationcurrent-reducing layer 230 is fabricated at the interface between anelectrode and the variable resistance layer 206 to passivate the defectsfound at the interface of the electrode 210 and the variable resistancelayer 206. Because the number of defects can vary from one fabricatedmemory device to the next, and from one region of the substrate on whichthe device is fabricated to another, the variability of the deviceperformance can vary from device to device, and from one region of thesubstrate to another.

Therefore, by fabricating the current-reducing layer 230 adjacent thevariable resistance layer 206, which reduces the number of interfacialdefects and passivates the interface surface, the device performancevariability across a fabricated integrated circuit structure (e.g.,array of fabricated devices) can be greatly reduced.

In addition, better data retention can be achieved through passivatingthe interface of the electrodes and the variable resistance layer 206.In this sense, passivation of the interface prevents trapping of chargedspecies during switching of the variable resistance layer 206, whichprevents degradation of switching current and voltage during bistableswitching operations of the variable resistance layer 206.

In addition, the current-reducing layer 230 provides an improveddiffusion barrier between the electrodes and the variable resistancelayer 206. For example, during formation of the variable resistancelayer 206 (e.g., HfO₂), oxygen atoms may diffuse into the surface of theelectrode (e.g., polysilicon) and form a low quality silicon oxidelayer, which may hinder the flow of current into the variable resistancelayer 206 resulting in elevated forming and/or switching currents andvoltages. The addition of the current-reducing layer 230 provides adiffusion barrier between the electrodes and the variable resistancelayer 206, resulting in a higher quality interface between the twolayers, and thus improved electrical properties.

The foregoing is merely illustrative of the principles of this inventionand various modifications can be made by those skilled in the artwithout departing from the scope and spirit of the invention as definedby the claims that follow.

1. A memory device, comprising: a nonvolatile memory element comprisinga variable resistance layer; a current-reducing layer formed as aportion of the variable resistance layer; and a current-limiting layerdisposed adjacent the variable resistance layer, wherein thecurrent-limiting layer has a breakdown voltage that exceeds a breakdownvoltage of the variable resistance layer.
 2. The memory device of claim1, further comprising a current-steering element coupled to the variableresistance layer.
 3. The memory device of claim 3, wherein an electricalresistance of the current-limiting layer is between about 75% and about125% of an electrical resistance of the current steering element whencurrent is flowing through the current steering element.
 4. The memorydevice of claim 1, wherein the current-limiting layer comprises amaterial selected from the group consisting of polysilicon, dopedsemiconductor materials, dielectric materials, metal nitrides,tantalum-containing materials, titanium-containing materials, siliconnitride, tantalum nitride, titanium nitride, hafnium nitride, germanium(Ge)-containing materials, gallium arsenide, and combinations thereof.5. The memory device of claim 1, wherein the current-reducing layercomprises a hafnium oxide material and a dopant selected from the groupconsisting of aluminum and zirconium.
 6. The memory device of claim 1,wherein the current-reducing layer comprises a silicon oxide-containinglayer.
 7. The memory device of claim 1, wherein the current-reducinglayer comprises a high-k material layer.
 8. The memory device of claim7, wherein the high-k material layer comprises a material selected fromthe group consisting of aluminum oxide, zirconium oxide, siliconoxynitride, and combinations thereof.
 9. A memory device comprising: anonvolatile memory element comprising a variable resistance layer; acurrent-reducing layer formed into a portion of the variable resistancelayer; and a current-limiting layer disposed adjacent the variableresistance layer, wherein: the variable resistance layer comprises ametal oxide material and the current-reducing layer comprises the metaloxide and a dopant, and the current-limiting layer has a breakdownvoltage that exceeds a breakdown voltage of the variable resistancelayer.
 10. The memory device of claim 9, wherein the dopant is selectedfrom the group consisting of aluminum, zirconium, and combinationsthereof.
 11. The memory device of claim 9, wherein the current-reducinglayer comprises a hafnium oxide material.
 12. A method of forming anonvolatile memory device, the method comprising: depositing a variableresistance layer over a surface of a substrate; forming acurrent-reducing layer as a part of the variable resistance layer; anddepositing a current-limiting layer adjacent the variable resistancelayer, wherein the current-limiting layer has a breakdown voltage thatexceeds a breakdown voltage of the variable resistance layer.
 13. Themethod of claim 12, further comprising: forming a current-steeringelement coupled to the variable resistance layer; and adjusting aresistivity of the current-limiting layer such that an electricalresistance of the current-limiting layer is between about 75% and about125% of an electrical resistance of the current steering element whencurrent is flowing through the current-steering element.
 14. The methodof claim 12, wherein the current-reducing layer comprises a siliconoxide-material.
 15. The method of claim 12, wherein the current-reducinglayer comprises a hafnium oxide material and a dopant selected from thegroup consisting of aluminum and zirconium.
 16. The method of claim 12,wherein the current-reducing layer comprises a high-k material layer.17. The method of claim 16, wherein the high-k material layer comprisesa material selected from the group consisting of aluminum oxide,zirconium oxide, silicon oxynitride, and combinations thereof.
 18. Amethod of forming a nonvolatile memory device having a nonvolatilememory element, the method comprising: depositing a variable resistancelayer over a surface of a substrate; forming a current-reducing layerinto a portion of the variable resistance layer by adding a dopantduring the deposition of the variable resistance layer; and depositing acurrent-limiting layer adjacent the variable resistance layer, whereinthe current-limiting layer has a breakdown voltage that exceeds abreakdown voltage of the variable resistance layer.
 19. The method ofclaim 18, wherein the dopant is a material selected from the groupconsisting of aluminum, zirconium, and combinations thereof.
 20. Themethod of claim 18, wherein the current-reducing layer comprises ahafnium oxide material.